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R01UH0823EJ0100 Rev.1.00 Page 1391 of 1823

Jul 31, 2019

RX23W Group 38. Serial Peripheral Interface (RSPIa)

(5) RSPCK Delay (t1)

The RSPCK delay value of the RSPI in master mode depends on the SPCMDm.SCKDEN bit setting and the SPCKD

and determines an RSPCK delay value during serial transfer by using the SPCMDm.SCKDEN bit and SPCKD, as listed

Table 38.9. For a definition of RSPCK delay, refer to section 38.3.5, Transfer Format.

(6) SSL Negation Delay (t2)

The SSL negation delay value of the RSPI in master mode depends on the SPCMDm.SLNDEN bit setting and the

SSLND register setting. The RSPI determines the SPCMDm register to be referenced during serial transfer by pointer

control, and determines an SSL negation delay value during serial transfer by using the SPCMDm.SLNDEN bit and

SSLND, as listed in

Table 38.10. For a definition of SSL negation delay, refer to section 38.3.5, Transfer Format.

Table 38.9 Relationship among SCKDEN Bit, SPCKD, and RSPCK Delay Value

SPCMDm.SCKDEN Bit SPCKD.SCKDL[2:0] Bits RSPCK Delay Value

0 000b to 111b 1 RSPCK

1 000b 1 RSPCK

001b 2 RSPCK

010b 3 RSPCK

011b 4 RSPCK

100b 5 RSPCK

101b 6 RSPCK

110b 7 RSPCK

111b 8 RSPCK

Table 38.10 Relationship among SLNDEN Bit, SSLND, and SSL Negation Delay Value

SPCMDm.SLNDEN Bit SSLND.SLNDL[2:0] Bits SSL Negation Delay Value