Overview
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SWRU543–January 2019
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Universal Asynchronous Receivers/Transmitters (UARTs)
6.1 Overview
The CC32xx includes two universal asynchronous receivers/transmitters (UARTs) with the following
features:
• Programmable baud-rate generator allowing speeds up to 3 Mbps.
• Separate 16 × 8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading
• Programmable FIFO length, including 1-byte-deep operation providing conventional double-buffered
interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Line-break generation and detection
• Fully programmable serial interface characteristics
– 5, 6, 7, or 8 data bits
– Even, odd, stick, or no-parity bit generation and detection
– 1 or 2 stop bit generation
• RTS and CTS hardware flow support
• Standard FIFO-level and end-of-transmission interrupts
• Efficient transfers using micro-direct memory access controller (µDMA)
– Separate channels for transmit and receive
– Receive single request asserted when data are in the FIFO; burst request asserted at programmed
FIFO level
– Transmit single request asserted when there is space in the FIFO; burst request asserted at
programmed FIFO level
• System clock generates the baud clock.
6.1.1 Block Diagram
Figure 6-1 shows the UART module block diagram.
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