Overview
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SWRU543–January 2019
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SD Host Controller Interface
11.1 Overview
The Secure Digital Host (SD Host) controller on the CC32xx device provides an interface between a local
host (LH) such as a microprocessor controller (MCU) and an SD memory card, and handles SD
transactions with minimal LH intervention.
The SD host provides SD card access in 1-bit mode, and contends with SD protocol at transmission level,
data packing, adding cyclic redundancy checks (CRCs), start/end bit, and checking for syntactical
correctness. The application interface can send every SD command and either poll for the status of the
adapter or wait for an interrupt request. An interrupt request is returned in the case of exceptions, or to
provide a warning of the end of an operation. The controller can be configured to generate DMA requests
and work with minimum CPU intervention. Given the nature of integration of this peripheral on the CC32xx
platform, TI recommends that developers use peripheral library APIs to control and operate the block.
This section emphasizes understanding the SD host APIs provided in the CC32xx Software Development
Kit [Peripheral Library].
11.2 SD Host Features
• Full compliance with SD command and response sets, as defined in the SD memory card.
Specifications, v2.0. Including high-capacity (size >2GB) cards HC SD.
• Flexible architecture, allowing support for new command structure.
• 1-bit transfer mode specifications for SD cards
• Built-in 1024-byte buffer for read or write
– 512-byte buffer for both transmit and receive
– Each buffer is 32 bits wide × 128 words deep
• 32-bit-wide access bus to maximize bus throughput
• Single interrupt line for multiple interrupt source events
• Two slave DMA channels (one for TX, one for RX)
• Programmable clock generation
• Integrates an internal transceiver that allows a direct connection to the SD card without external
transceiver
• Supports configurable busy and response time-out
• Support for a wide range of card clock frequency with odd and even clock ratio. Maximum frequency
supported is 24 MHz.
11.3 1-Bit SD Interface
Figure 11-1 shows a block diagram of the SDHost Controller Interface.
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