Texas Instruments CC3235 SimpleLink Series - Page 516

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SWRU543–January 2019
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Power, Reset, and Clock Management
15.1 Overview
The CC32xx SoC incorporates a highly optimized on-chip power management unit capable of operating
directly from battery, without any external regulator.
The on-chip power management unit (PMU) includes a set of high-efficiency, fast transient response
DC/DC converters, LDOs, and reference voltage generators. The on-chip PMU is connected to the input
supply directly, and generates the internal voltages required by the different sections of the chip across
power modes. The PMU is tightly synchronized with the WLAN radio, and avoids interference during radio
receive and transmit operations.
The input supply voltage at the chip pin supports a range of 2.1 V to 3.6 V for active operation. See the
CC3235S and CC3235SF SimpleLink™ Wi-Fi
®
, Dual-Band, Single-Chip Solution data sheet for electrical
details.
15.1.1 Power Management Unit (PMU)
The PMU includes the following key modules:
• Dig-DCDC: Generates 0.9-V to 1.2-V regulated output for digital core logic.
• ANA1-DCDC: Generates 1.8-V to 1.9-V regulated output for analog and RF.
• PA-DCDC: Generates 1.8-V to 1.9-V, and 2.3-V regulated output for WLAN transmit power amplifier.
• Precision voltage reference
• Supply brownout monitor:
– Brownout level for wide-voltage mode: 2.1 V
• 32.768-kHz crystal oscillator:
– Generates precision 32.768 kHz for RTC and WLAN power-save protocol timing.
– Supports feeding an external square wave 32.768-kHz clock in place of crystal.
• 32-kHz RC oscillator for chip start-up: The 32.768-kHz crystal oscillator requires 1.1 second to become
stable after first-time power up or chip reset (such as nRESET). Until the slow crystal clock is stable,
the system uses the alternate RC slow-clock.
• Hibernate controller: Implements the lowest current sleep mode of the chip (hibernate mode), and
consists of the following functions:
– Chip wake-up controller
– RTC counter and RTC-based wakeup
– GPIO monitor and GPIO-based wakeup
– 2 × 32-bit general-purpose direct-battery powered retention register
– Accessible from application processor through SoC-level interconnect
– Manages the PMU and I/Os when core digital is powered off
• PMU controller:
– Controls all the low-level real-time sequencing of the DC/DCs, LDOs, and references
– Implements the low-level sequences associated with sleep mode transitions
– Not directly accessible from the application processor
– PMU state transitions are initiated by control signals from the PRCM.
See the CC3235S and CC3235SF SimpleLink™ Wi-Fi
®
, Dual-Band, Single-Chip Solution data sheet for
the chip wake-up sequence and timing parameters.