www.ti.com
Functional Description
63
SWRU543–January 2019
Submit Documentation Feedback
Copyright © 2019, Texas Instruments Incorporated
Cortex
®
-M4 Processor
exception from the same source.
2.2.4.2 Exception Types
The exception types follow:
• Reset: Reset is invoked on power up or a warm reset. The exception model treats reset as a special
form of exception. When reset is asserted, the operation of the processor stops, potentially at any point
in an instruction. When reset is deasserted, execution restarts from the address provided by the reset
entry in the vector table. Execution restarts as privileged execution in thread mode.
• NMI: A nonmaskable interrupt (NMI) can be signaled using the NMI signal, or triggered by software
using the Interrupt Control and State (INTCTRL) register. This exception has the highest priority other
than reset. NMI is permanently enabled and has a fixed priority of –2. NMIs cannot be masked or
prevented from activation by any other exception or preempted by any exception other than reset. NMI
in the CC32xx is reserved for the internal system, and is not available for application usage.
• Hard Fault: A hard fault is an exception that occurs because of an error during exception processing,
or because an exception cannot be managed by any other exception mechanism. Hard faults have a
fixed priority of –1, meaning they have higher priority than any exception with configurable priority.
• Memory Management Fault: A memory-management fault is an exception that occurs because of a
memory-protection-related fault, including access violation and no match. The MPU or the fixed-
memory protection constraints determine this fault, for both instruction and data memory transactions.
This fault is used to abort instruction accesses to Execute Never (XN) memory regions, even if the
MPU is disabled.
• Bus Fault: A bus fault is an exception that occurs because of a memory-related fault for an instruction
or data memory transaction such as a prefetch fault or a memory access fault. This fault can be
enabled or disabled.
• Usage Fault: A usage fault is an exception that occurs because of a fault related to instruction
execution, such as:
– An undefined instruction
– An illegal unaligned access
– Invalid state on instruction execution
– An error on exception return. An unaligned address on a word or halfword memory access or
division by zero can cause a usage fault when the core is properly configured.
• SVCall: A supervisor call (SVC) is an exception that is triggered by the SVC instruction. In an OS
environment, applications can use SVC instructions to access OS kernel functions and device drivers.
• Debug Monitor: This exception is caused by the debug monitor (when not halting). This exception is
active only when enabled. This exception does not activate if it is a lower priority than the current
activation.
• PendSV: PendSV is a pendable, interrupt-driven request for system-level service. In an OS
environment, use PendSV for context switching when no other exception is active. PendSV is triggered
using the INTCTRL register.
• SysTick: A SysTick exception is an exception that the system timer generates when it reaches zero
when enabled to generate an interrupt. Software can also generate a SysTick exception using the
INTCTRL register. In an OS environment, the processor can use this exception as system tick.
• Interrupt (IRQ): An interrupt, or IRQ, is an exception signaled by a peripheral or generated by a
software request and fed through the NVIC (prioritized). All interrupts are asynchronous to instruction
execution. In the system, peripherals use interrupts to communicate with the processor. Table 2-7 lists
the interrupts on the CC32xx application processor
For an asynchronous exception, other than reset, the processor can execute another instruction between
when the exception is triggered and when the processor enters the exception handler.
Privileged software can disable the exceptions that Table 2-6 lists as having configurable priority (see the
SYSHNDCTRL register and the DIS0 register).
For more information about hard faults, memory management faults, bus faults, and usage faults, see
Section 2.2.5.
To Next Page
Loading...
