DES Block Diagram
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SWRU543–January 2019
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Data Encryption Standard Accelerator (DES)
18.2.3 Register Interface
The Register Interface block performs all address decoding and control; however, not all registers are
available in this block. The context and data input registers are in the DES engine.
18.2.4 DES Enginer
The DES-buffered engine consists of the following major functional blocks:
• Cipher core: the DES algorithm
• Mode control FSM: manages the data flow to and from the DES buffered engine and starts each
encrypt or decrypt operation.
• DES feedback mode block: the logic that implements the various feedback modes supported by the
DES buffered engine
18.2.4.1 Mode Control FSM
The mode control FSM manages the data flow to and from the DES engine. This block also sends a start
pulse to the encrypt/decrypt core and triggers the core to use the new mode keys when a new context is
needed. This module also controls the 3DES operation, such that the DES core module is triggered three
times (with different keys) before the result data becomes available.
18.2.4.2 DES Feedback Mode Block
The DES feedback mode block buffers the input and output blocks and contains all logic to implement the
3DES and various feedback modes. See the FIPS-81 document for details on the ECB, CBC, and CFB
modes of operation.
By itself, the DES cipher core outputs data compliant for ECB encryption. However, most applications use
DES with feedback. Feedback provides additional security by randomizing repeated patterns in the
plaintext, which could otherwise be exploited to attack the ciphertext. The DES buffered engine supports
ECB, CBC, and CFB modes of operations for the DES and 3DES algorithm.
3DES mode performs the DES algorithm three times on a single block and uses a different key for each
invocation of the DES algorithm, greatly increasing security of the ciphertext, but at a cost of three times
the reduction in throughput. The DES buffered engine implements a 3DES logic wrapper around the 2-
round DES core, enabling seamless 3DES encryption.
18.2.4.3 DES Cipher Core
The DES cipher core implements the DES algorithm as specified in the FIPS 46-3. The core operates on
the input block and performs the required substitution, shift, and mix operations. The core also applies the
correct key-scheduling.
Inherently, considerable parallelism is possible with the DES algorithm. This is exploited in two ways. For
high performance, the 64 bits composing the data block are processed concurrently (4-round
implementation). For low gate-count, resources are shared on both the main data and key paths (1-round
implementation).
A fundamental component of the DES algorithm is the substitution box (S-Box). The S-Box provides a
unique 4-bit output for each 6-bit input. The S-Box design is a primary factor for both performance and
gate count. The DES cipher core has a standard look-up table S-Box that allows room for the synthesizer
to optimize on timing or gate count.
18.3 DES-Supported Modes of Operation
18.3.1 ECB Feedback Mode
Figure 18-2 shows the basic ECB feedback mode of operation, where the input data is passed directly to
the basic cryptographic core and the output of the cryptographic core is passed directly to the output
buffer. For decryption, the DES core operates in reverse, meaning the decrypt key sequence is used for
the data processing, where encryption uses the encrypt key sequence.
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