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SHA/MD5 Functional Description
701
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
SHA/MD5 Accelerator
19.1.3.2.2 Closing a Hash
The amount of data to hash is not necessarily a multiple of 64 bytes. In this case, the CLOSE_HASH bit in
the SHAMD5_MODE register must be set to append padding so that the message size becomes a
multiple of 64 bytes. See the previous MD5 algorithm for more information on padding.
The module is fed with a 64-byte block of data, if enough data is available. However, a pad is appended
on the last block of data, which can result in the creation of an extra 64-byte block.
The one or two last blocks that contain the padding are processed the same way as the other blocks.
Hash completion is then indicated in the same way as for a new hash, and the 128-bit result can be read
in the digest registers. The SHAMD5_DIGESTCOUNT register returns restored digest count and length
when it is read, and hashing completes.
19.1.3.3 Generating a Software Interrupt
If the PIT_EN bit is 1 in the SHAMD5_SYSCONFIG register, an interrupt is generated at the completion of
the hash by the following steps:
1. Receive last block of data (= 64 bytes). The number of data bytes defined by the SHAMD5_LENGTH
register is received in the digest registers, from SHAMD5_ODIGEST_A/SHAMD5_IDIGEST_A to
SHAMD5_ODIGEST_H/SHAMD5_IDIGEST_H.
2. If required, apply padding to the last block of data.
3. Hash the last block of data (80 cycles in SHA-1 mode and 64 cycles in MD5, SHA-224, and SHA-256
modes).
4. If required, add an extra 64-byte block of data to complete the padding.
5. Hash this extra block of data (80 cycles in SHA-1 mode and 64 cycles in MD5, SHA-224, and SHA-256
modes).
6. An interrupt is generated (active low).
19.1.4 SHA/MD5 Programming Guide
This section covers the hardware programming sequences for configuration and use of the SHA/MD5
module.
19.1.4.1 Global Initialization
19.1.4.1.1 Surrounding Modules Global Initialization
The following list describes the requirements for initializing the SHAMD5 and associated modules:
1. Enable the clock to cryptography module (that includes AES) by setting the R0 bit in the
CRYPTOCLKEN register in the application reset and clock management module (physical address:
0x4402 50B8)
2. Configure the SHA µDMA channels for Context In, Context Out, Data In, or Data Out by programming
the appropriate encoding value in the DMA Channel Map Select n (DMA_CHMAPn) register in the
µDMA module.
3. If the SHA channels are configured in the µDMA, enable the required SHA DMA requests by
programming bits [9:5] of the SHAMD5_SYSCONFIG register, in addition to the completion interrupts
in the SHA DMA Interrupt Mask (DTHE_SHA_IM) register, CRC, and cryptographic modules offset
0x020.
19.1.4.1.2 Starting a New HMAC using the SHA-1 Hash Function and HMAC Key Processing
The following procedure is used to begin a new HMAC operation, starting from initial digest values.
1. Load the key value in the SHAMD5_ODIGEST_A/SHAMD5_IDIGEST_A to
SHAMD5_ODIGEST_H/SHAMD5_IDIGEST_H registers.
2. Pad the rest of the SHA _ODIGEST_x and SHAMD5_IDIGEST registers with zeros.
3. Load the message in the SHAMD5_DATA_n_IN FIFO registers.
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