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Texas Instruments CC3235 SimpleLink Series - Page 753

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Functional Description
753
SWRU543January 2019
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Copyright © 2019, Texas Instruments Incorporated
Cyclical Redundancy Check (CRC)
20.1 Functional Description
The following sections describe the features of CRC.
20.1.1 CRC Support
The purpose of the CRC engine is to accelerate CRC and TCP checksum operation. The result of the
CRC operation is a 32- and 16-bit signature that checks the sanity of data. The required mode of
operation is selected through the TYPE bit in the CRC Control (CRCCTRL) register, offset 0xC00.
The CRC module contains all of the control registers to which the input context interfaces. Because CRC
calculations are a single cycle, when data is written to the CRC Data Input (CRCDIN) register, the result of
CRC/CSUM is updated in the CRC SEED/Context (CRCSEED) register, offset 0xC10. The input data is
computed by the selected CRC polynomial or CSUM.
20.1.1.1 CRC Checksum Engine
Software can offload the CRC and checksum task to the CRC checksum engine accelerator. The
accelerator has registers that must be programmed to initiate processing. These registers should be fed
with data to calculate CRC/CSUM.
The starting seed for the CRC and checksum operation is programmed in the CRC SEED/Context
(CRCSEED) register at offset 0xC10. Depending on the encoding of the INIT field in the CRCCTRL
register, the value of the SEED field can initialized to any one of the following:
A unique context value written to the CRCSEED register (INIT=0x0)
All 0s (INIT=0x2)
All 1s (INIT=0x3)
When the operation is complete, software should read the result from the CRC Post Processing Result
(CRCRSLTPP) register, offset 0xC18.
20.1.1.2 Data Size
The CRC module supports data being fed 32-bit words and 8 bits at a time, and can dynamically switch
back and forth. The data size is configured by programming the SIZE bit in the CRCCTRL register, offset
0xC00.
Because CRC is a division on a long stream of bits, the application must consider the bit order. When
processing message data that is read out by words, bit order is not an issue. For example, if the data
value in the message is 0x12345678, the most significant 8 bytes is 0x12 (00010010 in binary). If the data
is processed as bytes, 0x12, 0x34, 0x56, and 0x78 are copied into memory in that order and the word is
stored as 0x78563412, where 0x12 is written as byte 0, 0x34 is written as byte 1, and so forth.

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