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SWRU543–January 2019
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-M4 Peripherals
Table 3-24. FAULTSTAT Register Field Descriptions (continued)
Bit Field Type Reset Description
15 BFARV R/W1C 0h
Bus Fault Address Register Valid
This bit is set after a bus fault, where the address is known. Other
faults can clear this bit, such as a memory management fault
occurring later. If a bus fault occurs and is escalated to a hard fault
because of priority, the hard fault handler must clear this bit. This
action prevents problems if returning to a stacked active bus fault
handler whose FAULTADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
0h = The value in the Bus Fault Address (FAULTADDR) register is
not a valid fault address.
1h = The FAULTADDR register is holding a valid fault address.
14 RESERVED R 0h
13 BLSPERR R/W1C 0h
N/A
12 BSTKE R/W1C 0h
Stack Bus Fault
When this bit is set, the SP is still adjusted but the values in the
context area on the stack might be incorrect. A fault address is not
written to the FAULTADDR register. This bit is cleared by writing a 1
to it.
0h = No bus fault has occurred on stacking for exception entry.
1h = Stacking for an exception entry has caused one or more bus
faults.
11 BUSTKE R/W1C 0h
Unstack Bus Fault
This fault is chained to the handler. Thus, when this bit is set, the
original return stack is still present. The SP is not adjusted from the
failing return, a new save is not performed, and a fault address is not
written to the FAULTADDR register. This bit is cleared by writing a 1
to it.
0h = No bus fault has occurred on unstacking for a return from
exception.
1h = Unstacking for a return from exception has caused one or more
bus faults.
10 IMPRE R/W1C 0h
Imprecise Data Bus Error
When this bit is set, a fault address is not written to the FAULTADDR
register. This fault is asynchronous. Therefore, if the fault is detected
when the priority of the current process is higher than the bus fault
priority, the bus fault becomes pending and becomes active only
when the processor returns from all higher-priority processes. If a
precise fault occurs before the processor enters the handler for the
imprecise bus fault, the handler detects that both the IMPRE bit is
set and one of the precise fault status bits is set. This bit is cleared
by writing a 1 to it.
0h = An imprecise data bus error has not occurred.
1h = A data bus error has occurred, but the return address in the
stack frame is not related to the instruction that caused the error.
9 PRECISE R/W1C 0h
Precise Data Bus Error
When this bit is set, the fault address is written to the FAULTADDR
register. This bit is cleared by writing a 1 to it.
0h = A precise data bus error has not occurred.
1h = A data bus error has occurred, and the PC value stacked for
the exception return points to the instruction that caused the fault.
8 IBUS R/W1C 0h
Instruction Bus Error
The processor detects the instruction bus error on prefetching an
instruction, but sets this bit only if it attempts to issue the faulting
instruction. When this bit is set, a fault address is not written to the
FAULTADDR register. This bit is cleared by writing a 1 to it.
0h = An instruction bus error has not occurred.
1h = An instruction bus error has occurred.
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