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19
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
List of Figures
13-1. Architecture of the ADC Module in CC32xx........................................................................... 458
13-2. Operation of the ADC .................................................................................................... 459
13-3. ADC_CTRL Register ..................................................................................................... 461
13-4. ADC_CH0_IRQ_EN Register ........................................................................................... 462
13-5. ADC_CH2_IRQ_EN Register ........................................................................................... 463
13-6. ADC_CH4_IRQ_EN Register ........................................................................................... 464
13-7. ADC_CH6_IRQ_EN Register ........................................................................................... 465
13-8. ADC_CH0_IRQ_STATUS Register .................................................................................... 466
13-9. ADC_CH2_IRQ_STATUS Register .................................................................................... 467
13-10. ADC_CH4_IRQ_STATUS Register .................................................................................... 468
13-11. ADC_CH6_IRQ_STATUS Register .................................................................................... 469
13-12. ADC_DMA_MODE_EN Register ....................................................................................... 470
13-13. ADC_TIMER_CONFIGURATION Register............................................................................ 471
13-14. ADC_TIMER_CURRENT_COUNT Register .......................................................................... 471
13-15. CHANNEL0FIFODATA Register........................................................................................ 472
13-16. CHANNEL2FIFODATA Register........................................................................................ 472
13-17. CHANNEL4FIFODATA Register........................................................................................ 473
13-18. CHANNEL6FIFODATA Register........................................................................................ 473
13-19. ADC_CH0_FIFO_LVL Register......................................................................................... 474
13-20. ADC_CH2_FIFO_LVL Register......................................................................................... 475
13-21. ADC_CH4_FIFO_LVL Register......................................................................................... 476
13-22. ADC_CH6_FIFO_LVL Register......................................................................................... 477
13-23. ADC_CH_ENABLE Register ............................................................................................ 478
14-1. Camera Module Interfaces .............................................................................................. 488
14-2. Synchronization Signals and Frame Timing........................................................................... 489
14-3. Synchronization Signals and Data Timing............................................................................. 489
14-4. Different Scenarios of CAM_P_HS and CAM_P_VS ................................................................ 490
14-5. CAM_P_HS Toggles Between Pixels in Decimation................................................................. 490
14-6. Parallel Camera Interface State Machine ............................................................................. 491
14-7. FIFO Image Data Format................................................................................................ 491
14-8. Assertion and Deassertion of the DMA Request Signal............................................................. 494
14-9. CC_SYSCONFIG Register .............................................................................................. 497
14-10. CC_SYSSTATUS Register .............................................................................................. 498
14-11. CC_IRQSTATUS Register............................................................................................... 499
14-12. CC_IRQENABLE Register............................................................................................... 501
14-13. CC_CTRL Register ....................................................................................................... 503
14-14. CC_CTRL_DMA Register ............................................................................................... 505
14-15. CC_CTRL_XCLK Register .............................................................................................. 506
14-16. CC_FIFODATA Register................................................................................................. 507
15-1. Power Management Unit Configuration................................................................................ 517
15-2. Sleep Modes .............................................................................................................. 519
15-3. Power Management Control Architecture in CC32xx ................................................................ 521
15-4. CAMCLKCFG Register .................................................................................................. 531
15-5. CAMCLKEN Register .................................................................................................... 532
15-6. CAMSWRST Register.................................................................................................... 533
15-7. MCASPCLKEN Register................................................................................................. 534
15-8. MCASPSWRST Register ................................................................................................ 535
15-9. SDIOMCLKCFG Register................................................................................................ 536
15-10. SDIOMCLKEN Register.................................................................................................. 537
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