Texas Instruments CC3235 SimpleLink Series - Page 20

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20
SWRU543–January 2019
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List of Figures
15-11. SDIOMSWRST Register................................................................................................. 538
15-12. APSPICLKCFG Register................................................................................................. 539
15-13. APSPICLKEN Register .................................................................................................. 540
15-14. APSPISWRST Register.................................................................................................. 541
15-15. DMACLKEN Register .................................................................................................... 542
15-16. DMASWRST Register.................................................................................................... 543
15-17. GPIO0CLKEN Register .................................................................................................. 544
15-18. GPIO0SWRST Register ................................................................................................. 545
15-19. GPIO1CLKEN Register .................................................................................................. 546
15-20. GPIO1SWRST Register ................................................................................................. 547
15-21. GPIO2CLKEN Register .................................................................................................. 548
15-22. GPIO2SWRST Register ................................................................................................. 549
15-23. GPIO3CLKEN Register .................................................................................................. 550
15-24. GPIO3SWRST Register ................................................................................................. 551
15-25. GPIO4CLKEN Register .................................................................................................. 552
15-26. GPIO4SWRST Register ................................................................................................. 553
15-27. WDTCLKEN Register .................................................................................................... 554
15-28. WDTSWRST Register.................................................................................................... 555
15-29. UART0CLKEN Register.................................................................................................. 556
15-30. UART0SWRST Register................................................................................................. 557
15-31. UART1CLKEN Register.................................................................................................. 558
15-32. UART1SWRST Register................................................................................................. 559
15-33. GPT0CLKCFG Register ................................................................................................. 560
15-34. GPT0SWRST Register................................................................................................... 561
15-35. GPT1CLKEN Register ................................................................................................... 562
15-36. GPT1SWRST Register................................................................................................... 563
15-37. GPT2CLKEN Register ................................................................................................... 564
15-38. GPT2SWRST Register................................................................................................... 565
15-39. GPT3CLKEN Register ................................................................................................... 566
15-40. GPT3SWRST Register................................................................................................... 567
15-41. MCASPCLKCFG0 Register ............................................................................................. 568
15-42. MCASPCLKCFG1 Register ............................................................................................. 569
15-43. I2CLCKEN Register ...................................................................................................... 570
15-44. I2CSWRST Register ..................................................................................................... 571
15-45. LPDSREQ Register....................................................................................................... 572
15-46. TURBOREQ Register .................................................................................................... 573
15-47. DSLPWAKECFG Register............................................................................................... 574
15-48. DSLPTIMRCFG Register ................................................................................................ 575
15-49. SLPWAKEEN Register................................................................................................... 576
15-50. SLPTMRCFG Register................................................................................................... 577
15-51. WAKENWP Register ..................................................................................................... 578
15-52. RCM_IS Register ......................................................................................................... 579
15-53. RCM_IEN Register ....................................................................................................... 580
16-1. Board Configuration to Use Pins 45 and 52........................................................................... 585
16-2. Board Configuration to Use Pins 45 and 52 as Digital Signals..................................................... 586
16-3. I/O Pad Data and Control Path Architecture in CC32xx............................................................. 606
16-4. Wake on Pad for Hibernate Mode...................................................................................... 609
17-1. AES Block Diagram ...................................................................................................... 613
17-2. AES - ECB Feedback Mode............................................................................................. 616