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SWRU543–January 2019
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List of Tables
13-5. ADC_CH2_IRQ_EN Register Field Descriptions..................................................................... 463
13-6. ADC_CH4_IRQ_EN Register Field Descriptions..................................................................... 464
13-7. ADC_CH6_IRQ_EN Register Field Descriptions..................................................................... 465
13-8. ADC_CH0_IRQ_STATUS Register Field Descriptions .............................................................. 466
13-9. ADC_CH2_IRQ_STATUS Register Field Descriptions .............................................................. 467
13-10. ADC_CH4_IRQ_STATUS Register Field Descriptions .............................................................. 468
13-11. ADC_CH6_IRQ_STATUS Register Field Descriptions .............................................................. 469
13-12. ADC_DMA_MODE_EN Register Field Descriptions ................................................................. 470
13-13. ADC_TIMER_CONFIGURATION Register Field Descriptions ..................................................... 471
13-14. ADC_TIMER_CURRENT_COUNT Register Field Descriptions.................................................... 471
13-15. CHANNEL0FIFODATA Register Field Descriptions ................................................................. 472
13-16. CHANNEL2FIFODATA Register Field Descriptions ................................................................. 472
13-17. CHANNEL4FIFODATA Register Field Descriptions ................................................................. 473
13-18. CHANNEL6FIFODATA Register Field Descriptions ................................................................. 473
13-19. ADC_CH0_FIFO_LVL Register Field Descriptions................................................................... 474
13-20. ADC_CH2_FIFO_LVL Register Field Descriptions................................................................... 475
13-21. ADC_CH4_FIFO_LVL Register Field Descriptions................................................................... 476
13-22. ADC_CH6_FIFO_LVL Register Field Descriptions................................................................... 477
13-23. ADC_CH_ENABLE Register Field Descriptions...................................................................... 478
13-24. ulChannel Tags ........................................................................................................... 479
13-25. ulIntFlags Tags............................................................................................................ 480
14-1. Image Sensor Interface Signals ........................................................................................ 489
14-2. Ratio of the XCLK Frequency Generator .............................................................................. 493
14-3. Camera Registers ........................................................................................................ 496
14-4. CC_SYSCONFIG Register Field Descriptions........................................................................ 497
14-5. CC_SYSSTATUS Register Field Descriptions........................................................................ 498
14-6. CC_IRQSTATUS Register Field Descriptions ........................................................................ 499
14-7. CC_IRQENABLE Register Field Descriptions ........................................................................ 501
14-8. CC_CTRL Register Field Descriptions................................................................................. 503
14-9. CC_CTRL_DMA Register Field Descriptions ......................................................................... 505
14-10. CC_CTRL_XCLK Register Field Descriptions ........................................................................ 506
14-11. CC_FIFODATA Register Field Descriptions .......................................................................... 507
15-1. Possible PM State Combinations of Application Processor and Network Subsystem (NWP+WLAN) ........ 520
15-2. Peripheral Macro Table .................................................................................................. 529
15-3. PRCM Registers .......................................................................................................... 529
15-4. CAMCLKCFG Register Field Descriptions ............................................................................ 531
15-5. CAMCLKEN Register Field Descriptions .............................................................................. 532
15-6. CAMSWRST Register Field Descriptions ............................................................................. 533
15-7. MCASPCLKEN Register Field Descriptions........................................................................... 534
15-8. MCASPSWRST Register Field Descriptions.......................................................................... 535
15-9. SDIOMCLKCFG Register Field Descriptions ......................................................................... 536
15-10. SDIOMCLKEN Register Field Descriptions ........................................................................... 537
15-11. SDIOMSWRST Register Field Descriptions........................................................................... 538
15-12. APSPICLKCFG Register Field Descriptions .......................................................................... 539
15-13. APSPICLKEN Register Field Descriptions ............................................................................ 540
15-14. APSPISWRST Register Field Descriptions ........................................................................... 541
15-15. DMACLKEN Register Field Descriptions .............................................................................. 542
15-16. DMASWRST Register Field Descriptions ............................................................................. 543
15-17. GPIO0CLKEN Register Field Descriptions............................................................................ 544