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Functional Overview
43
SWRU543–January 2019
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Architecture Overview
1.3.1.3 Nested Vector Interrupt Controller (NVIC)
The CC32xx device includes the Arm
®
NVIC. The NVIC and Cortex
®
-M4 prioritize and handle all
exceptions in handler mode. The processor state is automatically stored to the stack on an exception and
automatically restored from the stack at the end of the interrupt service routine (ISR). The interrupt vector
is fetched in parallel to the state saving, thus enabling efficient interrupt entry. The processor supports tail-
chaining, meaning that back-to-back interrupts can be performed without the overhead of state saving and
restoration. The NVIC and Cortex
®
-M4 processor prioritize and handle all exceptions in handler mode. The
NVIC and the processor core interface are closely coupled to enable low-latency interrupt processing and
efficient processing of late-arriving interrupts. The NVIC maintains knowledge of the stacked, or nested,
interrupts to enable tail-chaining of interrupts.
Key features follow:
• Exceptional interrupt handling through hardware implementation of required register manipulations
• Deterministic, fast interrupt processing: always 12 cycles, or just 6 cycles with tail-chaining
• Programmable priority level for each interrupt
• Low-latency interrupt and exception handling
• Level and pulse detection of interrupt signals
• Grouping of interrupts into group priority and subpriority interrupts
1.3.1.4 System Control Block
The system control block (SCB) provides system implementation information and system control, including
configuration, control, and reporting of system exceptions.
1.3.2 Memory
1.3.2.1 On-Chip SRAM
The CC32xx device has up to 256KB of zero wait state, on-chip SRAM, to which application programs are
downloaded and executed. The SRAM is used for both code and data, and is connected to the Multilayer-
AHB bus-matrix of the chip. There is no restriction on relative size or partitioning of code and data on the
micro-direct memory access (μDMA) controller except the lower 16KBs of SRAM.
The micro-direct memory access (µDMA) controller can transfer data to and from SRAM and various
peripherals. The SRAM banks implement an advanced 4-way interleaved architecture, which almost
eliminates the performance penalty when DMA and processor simultaneously access the SRAM.
Internal RAM has selective retention capability during low-power deep-sleep (LPDS) mode. Based on
need, during LPDS mode the application can choose to retain 256KB, 192KB, 128KB, or 64KB. Retaining
the memory during low-power mode provides a faster wakeup. TI provides an easy-to-use power-
management framework for processor and peripheral context save and restore mechanism based on
SRAM retention. For more information, see CC3200 Power Management Framework.
1.3.2.2 ROM
CC32xx comes with factory programmed zero-wait-state ROM with the following firmware components:
• Device initialization
• Bootloader
• Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces
When the CC32xx powers up, or the chip reset is released or returns from hibernate mode, the device
initialization procedure is executed first. After the chip hardware has been correctly configured, the
bootloader is executed, which loads the application code from nonvolatile memory into on-chip SRAM and
makes a jump to the application code entry point.
The CC32xx DriverLib is a software library that controls on-chip peripherals. The library performs both
peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support.
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