Functional Overview
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SWRU543–January 2019
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Architecture Overview
The ROM DriverLib provides a rich set of drivers for peripheral and chip. The DriverLib is aimed at
reducing application development time and improving solution robustness. TI recommends that
applications make extensive use of the DriverLib APIs to optimize memory and MIPS requirement of end
applications.
1.3.2.3 Flash Memory
The CC3235SF device comes with an on-chip flash memory of 1024KB, allowing application code to
execute in-place while freeing up SRAM to be used exclusively for read-write data. The flash memory is
used for code and constant data sections, and is directly attached to the ICODE/DCODE bus of the
Cortex
®
-M4 core. A 128-bit-wide instruction prefetch buffer allows maintaining maximum performance for
linear code, or loops that fit inside the buffer.
The flash memory is organized as 2-KB sectors that can be independently erased. Reads and writes can
be performed at word (32-bit) level.
1.3.3 Micro-Direct Memory Access Controller (µDMA)
The CC32xx MCU includes a micro-direct memory access (μDMA) controller. The µDMA controller
provides a way to offload data-transfer tasks from the Cortex
®
-M4 processor, allowing more efficient use
of the processor and the available bus bandwidth. The µDMA controller can perform transfers between
memory and peripherals; it has dedicated channels for each supported on-chip module. The µDMA
controller can be programmed to automatically perform transfers between peripherals and memory as the
peripheral is ready to transfer more data.
The µDMA controller provides the following features:
• 32 configurable channels
• 80-MHz operation
• Support for memory-to-memory, memory-to-peripheral, and peripheral-to-memory in multiple transfer
modes
– Basic and simple transfer scenarios
– Ping-pong for continuous data flow
– Scatter-gather for a programmable list of arbitrary transfers initiated from a single request
• Highly flexible and configurable channel operation
– Independently configured and operated channels
– Dedicated channels for supported on-chip modules
– One channel each for receive and transmit path for bidirectional modules
– Dedicated channel for software-initiated transfers
– Per-channel configurable bus arbitration scheme
– Software-initiated requests for any channel
• Two levels of priority
• Design optimizations for improved bus access performance between the µDMA controller and the
processor core
– µDMA controller access subordinate to core access
– Simultaneous concurrent access
• Data sizes of 8, 16, and 32 bits
• Transfer size is programmable in binary steps from 1 to 1024
• Source and destination address increment size of byte, halfword, word, or no increment
• Maskable peripheral requests
• Interrupt on transfer completion, with a separate interrupt per channel
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