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Functional Overview
45
SWRU543–January 2019
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Architecture Overview
1.3.4 General-Purpose Timer (GPT)
The CC32xx includes 4 instances of 32-bit user-programmable general-purpose timers (GPTs). GPTs
count or time external events that drive the timer input pins. Each GPT module (GPTM) block provides two
16-bit timers or counters that can be configured to operate independently as timers or event counters, or
configured to operate as one 32-bit timer. The GPTM contains GPTM blocks with the following functional
options:
• Operating modes:
– 16- or 32-bit programmable one-shot timer
– 16- or 32-bit programmable periodic timer
– 16-bit GPT with an 8-bit prescaler
– 16-bit input-edge count or time-capture modes
– 16-bit pulse-width modulation (PWM) mode with software-programmable output inversion of the
PWM signal
• Count up or down
• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the ISR
• Can trigger efficient transfers using the µDMA.
– Dedicated channel for each timer
– Burst request generated on timer interrupt
1.3.5 Watchdog Timer (WDT)
The watchdog timer (WDT) in the CC32xx restarts the system when it gets stuck due to an error and does
not respond as expected. The WDT can be configured to generate an interrupt to the MCU on its first
time-out, and to generate a reset signal on its second time-out. Once the WDT is configured, the lock
register can be written to prevent the timer configuration from being inadvertently altered.
The WDT provides the following features:
• 32-bit down-counter with a programmable load register
• Programmable interrupt generation logic with interrupt masking
• Lock register protection from runaway software
• Reset generation logic
1.3.6 Multichannel Audio Serial Port (McASP)
The CC32xx includes a configurable multichannel audio serial port (McASP) for glue-less interfacing to
audio codec and DAC (speaker drivers). The audio port has two serializers or deserializers that can be
individually enabled to either transmit or receive and operate synchronously. Key features follow:
• Two stereo I2S channels
– One stereo receive and one stereo transmit lines
– Two stereo transmit lines
• Programmable clock and frame-sync polarity (rising or falling edge)
• Programmable word length (bits per word): 16 and 24 bits
• Programmable fractional divider for bit-clock generation, up to 9 MHz
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