Functional Overview
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SWRU543–January 2019
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Architecture Overview
1.3.13 Parallel Camera Interface
The CC32xx includes an 8-bit parallel camera port to enable image sensor-based applications.
1.3.14 Debug Interface
The CC32xx supports both IEEE Standard 1149.1 JTAG (4-wire) and the low-pin-count Arm
®
SWD (2-
wire) debug interfaces. Depending on the board-level configuration of the sense-on-power pull resistors,
by default the chip powers up with either the 4-wire JTAG or the 2-wire SWD interface.
As shown in Figure 1-1, the 4-wire JTAG signals from the chip pins are routed through an IcePick module.
TAPs other than the application MCU are reserved for TI production testing. A sequence that selects the
TAP must be sent to the device to connect to the Arm
®
Cortex
®
-M4 JTAG TAP. The 2-wire mode,
however, directly routes the Arm
®
SWD-TMS and SWD-TCK pins directly to the respective chip pins.
1.3.15 Hardware Cryptography Accelerator
The secure variant of the CC32xx includes a suite of high-throughput, state-of-the-art hardware
accelerators for fast computation of ciphers (AES, DES, 3-DES), hashing (SHA, MD5), and CRC
algorithms by the application. It is also referred to as the data hashing and transform engine (DTHE).
1.3.16 Clock, Reset, and Power Management
The CC32xx system-on-chip includes the necessary clock and power management functionalities to build
a stand-alone, battery-operated low-power solution. Key features follow:
• Primary clocks
– Slow clock: 32.768 kHz (±250 ppm)
• Used in RTC, Wi-Fi
®
beacon listen timing in low-power idle mode and some of the chip internal
sequencing
• On-chip, low-power 32-kHz crystal oscillator
• Support for externally-fed 32.768-kHz clock
• On-chip 32-kHz RC oscillator for initial wakeup
– Fast clock: 40 MHz (±20 ppm)
• Used in Wi-Fi
®
radio and MCU
• On-chip low phase-noise 40-MHz crystal oscillator
• Support for externally fed, clean 40-MHz clock (such as TCXO)
• System and peripheral clocks are derived from internal PLL producing 240 MHz
• Flexible reset scheme
– The following resets are supported in CC32xx:
• External chip reset pin: the entire chip, including power management, is reset when the
nRESET pin is held low
• Reset on hibernate: the entire core is reset when the chip goes through a hibernate cycle
• Reset on watchdog: the application MCU is reset when the WDT expires
• Soft-reset: the application MCU is reset by software
– Complete system recovery from any scenario at which the scenario is stuck can be achieved by
using a combination of WDT reset and hibernate sleep.
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