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Functional Overview
49
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Architecture Overview
• On-chip power management
– Wide voltage mode: 2.1 V to 3.6 V
• Powered by battery (2×1.5 V) or a regulated 3.3-V supply
– A set of three on-chip high-efficiency DC/DC converters produce the internal module supply
voltages when needed. These switching converters and their frequency plan are optimized to
minimize interference to WLAN radio.
• DIG-DCDC: Produces 0.9 V to 1.2 V for the core digital logic
• ANA1-DCDC: Produces low-ripple 1.8-V supply for the analog and RF
• PA-DCDC: Produces regulated 1.8 V with extremely fast transient regulation for the WLAN RF
transmit power amplifier
– A set of low-dropout regulators (LDOs) is used in the radio subsystem to further regulate and filter
the ANA1-DCDC output before being fed to the analog circuits
– On-chip factory-trimmed accurate band-gap voltage reference ensures the regulator outputs are
stable across process and temperature
1.3.17 SimpleLink™ Subsystem
The SimpleLink™ subsystem provides fast, secured WLAN and Internet connections with 256-bit
encryption. The CC32xx device supports station, AP, and Wi-Fi Direct
®
modes. The device also supports
WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi
®
network processor includes an
embedded IPv6 TCP/IP stack.
This multiprocessor subsystem consists of:
• IPv6 network processor and Wi-Fi
®
driver
• 802.11 b/g/n/a MAC
• 802.11 b/g/n/a PHY
• 802.11 b/g/n/a radio
The SimpleLink™ subsystem is accessible from the application MCU over an asynchronous link, and can
be controlled through a complete set of SimpleLink™ host driver APIs provided as part of the ROM driver
library. The mode of usage is similar to that of an external MCU using the CC3120 device.
The co-location of the Wi-Fi
®
subsystem on the same die imposes a few restrictions on the application
MCU. These are covered in Chapter 15.
1.3.18 I/O Pads and Pin Multiplexing
The device makes extensive use of pin multiplexing to accommodate the large number of peripheral
functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled
using a combination of hardware configuration (at device reset) and register control.
The I/O pad and pin multiplexing sections feature flexible wide-voltage I/Os. Supported features include:
• Programmable drive strength of 2 mA, 4 mA, and 6 mA
• Open-drain mode
• Output buffer isolation
• Automatic output isolation during reset and hibernate
• Configurable pullup and pulldown (10 µA nominal)
• Software-configurable pad state retention during LPDS
• All digital I/Os are nonfail-safe
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