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Functional Description
281
SWRU543–January 2019
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SPI (Serial Peripheral Interface)
8.2.6.1 FIFO Buffer Enabled
The DMA read request line asserts when the channel is enabled, and the number of bytes defined in
SPI_XFERLEVEL[AFL] bit field is held in the FIFO buffer for the receive register of the channel. A DMA
read request can be individually masked with the DMAR bit of the SPI_CHCONF register. The DMA read
request line is deasserted on the first SPI word read completion of the receive register of the channel. No
new DMA request is asserted if the user has not performed the correct number of read accesses, as
defined by SPI_XFERLEVEL[AFL].
The DMA write request line asserts when the channel is enabled, and the number of bytes held in the
FIFO buffer is below the level defined by the SPI_XFERLEVEL[AEL] bit field. A DMA write request can be
individually masked with the DMAW bit of the SPI_CHCONF register.
8.2.7 Reset
The module can be reset by software through the SoftReset bit of the SPI_SYSCONFIG register. The
SPI_SYSCONFIG register is not sensitive to software reset. The SoftReset control bit is active high.
Hardware automatically resets the bit to 0.
A global ResetDone status bit is provided in the SPI_SYSCONFIG status register. The global ResetDone
status bit can be monitored by the software to check if the module is ready to use following a reset.
8.3 Initialization and Configuration
This section describes a GSPI module initialization and configuration example for both basic modes
supported to transmit and receive at 100000 kHz.
8.3.1 Basic Initialization
a. Enable the SPI module clock by invoking the following API:
PRCMPeripheralClkEnable(PRCM_GSPI,PRCM_RUN_MODE_CLK)
b. Set the pinmux to bring out the SPI signals to the chip boundary at desired location:
PinTypeSPI(<pin_no>, <mode>).
c. Soft reset the module:
SPIReset(GSPI_BASE)
8.3.2 Master Mode Operation Without Interrupt (Polling)
a. Configure the SPI with the following parameters:
• Mode: 4-pin/master
• Submode: 0
• Bit Rate: 100000 Hz
• Chip Select: Software-controlled/active high
• Word Length: 8 bits
SPIConfigSetExpClk(GSPI_BASE,PRCMPeripheralClockGet(PRCM_GSPI),
100000, SPI_MODE_MASTER,
SPI_SUB_MODE_0, (SPI_SW_CTRL_CS | SPI_4PIN_MODE|SPI_TURBO_OFF |
SPI_CS_ACTIVEHIGH |
SPI_WL_8))
b. Enable SPI channel for communication:
SPIEnable(GSPI_BASE)
c. Enable chip select:
SPICSEnable(GSPI_BASE)
d. Write new data into TX FIFO to transmit over the interface:
SPIDataPut(GSPI_BASE,<UserData>);
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