Texas Instruments CC3235 SimpleLink Series - Page 7

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7
SWRU543–January 2019
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Contents
12 Inter-Integrated Sound (I2S) Multichannel Audio Serial Port................................................... 401
12.1 Overview ................................................................................................................... 402
12.1.1 I2S Format....................................................................................................... 402
12.2 Functional Description.................................................................................................... 403
12.3 Programming Model...................................................................................................... 403
12.3.1 Clock and Reset Management................................................................................ 403
12.3.2 I2S Data Port Interface......................................................................................... 404
12.3.3 Initialization and Configuration................................................................................ 404
12.4 Peripheral Library APIs for I2S Configuration......................................................................... 406
12.4.1 Basic APIs for Enabling and Configuring the Interface .................................................... 406
12.4.2 APIs for Data Access if DMA is Not Used................................................................... 408
12.4.3 APIs for Setting Up, Handling Interrupts, or Getting Status from I2S Peripheral....................... 409
12.4.4 APIs to Control FIFO Structures Associated With I2S Peripheral........................................ 413
12.5 I2S Registers .............................................................................................................. 415
12.5.1 AFIFOREV Register (Offset = 0h) [reset = 0h] ............................................................. 417
12.5.2 WFIFOCTL Register (Offset = 10h) [reset = 1004h] ....................................................... 418
12.5.3 PDIR Register (Offset = 14h) [reset = 0h]................................................................... 419
12.5.4 RFIFOCTL Register (Offset = 18h) [reset = 1004h]........................................................ 421
12.5.5 RFIFOSTS Register (Offset = 1Ch) [reset = 0h]............................................................ 422
12.5.6 GBLCTL Register (Offset = 44h) [reset = 0h]............................................................... 423
12.5.7 RGBLCTL Register (Offset = 60h) [reset = 0h]............................................................. 425
12.5.8 RMASK Register (Offset = 64h) [reset = 0h]................................................................ 427
12.5.9 RFMT Register (Offset = 68h) [reset = 0h].................................................................. 428
12.5.10 AFSRCTL Register (Offset = 6Ch) [reset = 0h] ........................................................... 430
12.5.11 RTDM Register (Offset = 78h) [reset = 0h] ................................................................ 431
12.5.12 RINTCTL Register (Offset = 7Ch) [reset = 0h] ............................................................ 432
12.5.13 RSTAT Register (Offset = 80h) [reset = 0h] ............................................................... 434
12.5.14 RSLOT Register (Offset = 84h) [reset = 0h]............................................................... 436
12.5.15 REVTCTL Register (Offset = 8Ch) [reset = 0h] ........................................................... 437
12.5.16 XGBLCTL Register (Offset = A0h) [reset = 0h] ........................................................... 438
12.5.17 XMASK Register (Offset = A4h) [reset = 0h] .............................................................. 440
12.5.18 XFMT Register (Offset = A8h) [reset = 0h] ................................................................ 441
12.5.19 AFSXCTL Register (Offset = ACh) [reset = 0h] ........................................................... 443
12.5.20 ACLKXCTL Register (Offset = B0h) [reset = 60h] ........................................................ 444
12.5.21 AHCLKXCTL Register (Offset = B4h) [reset = 8000h] ................................................... 445
12.5.22 XTDM Register (Offset = B8h) [reset = 0h]................................................................ 446
12.5.23 XINTCTL Register (Offset = BCh) [reset = 0h]............................................................ 447
12.5.24 XSTAT Register (Offset = C0h) [reset = 0h]............................................................... 449
12.5.25 XSLOT Register (Offset = C4h) [reset = 17Fh] ........................................................... 451
12.5.26 XEVTCTL Register (Offset = CCh) [reset = 0h]........................................................... 452
12.5.27 SRCTLn Register (Offset = 180h) [reset = 0h] ............................................................ 453
12.5.28 XBUFn Register (Offset = 200h) [reset = 0h].............................................................. 455
12.5.29 RBUFn Register (Offset = 280h) [reset = 0h] ............................................................. 456
13 Analog-to-Digital Converter (ADC) ...................................................................................... 457
13.1 Overview ................................................................................................................... 458
13.2 Key Features .............................................................................................................. 458
13.3 ADC Register Mapping................................................................................................... 459
13.4 ADC_MODULE Registers ............................................................................................... 460
13.4.1 ADC Register Description ..................................................................................... 460
13.5 Initialization and Configuration ......................................................................................... 479
13.6 Peripheral Library APIs for ADC Operation ........................................................................... 479
13.6.1 Overview ......................................................................................................... 479
13.6.2 Configuring the ADC Channels ............................................................................... 479