Texas Instruments CC3235 SimpleLink Series - Page 6

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6
SWRU543–January 2019
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Contents
9.5.15 GPTMTAPMR Register (offset = 40h) [reset = 0h]......................................................... 339
9.5.16 GPTMTBPMR Register (offset = 44h) [reset = 0h]......................................................... 340
9.5.17 GPTMTAR Register (offset = 48h) [reset = FFFFFFFFh] ................................................. 341
9.5.18 GPTMTBR Register (offset = 4Ch) [reset = FFFFh] ....................................................... 342
9.5.19 GPTMTAV Register (offset = 50h) [reset = FFFFFFFFh] ................................................. 343
9.5.20 GPTMTBV Register (offset = 54h) [reset = FFFFh]........................................................ 344
9.5.21 GPTMDMAEV Register (offset = 6Ch) [reset = 0h] ........................................................ 345
10 Watchdog Timer ............................................................................................................... 347
10.1 Overview ................................................................................................................... 348
10.1.1 Block Diagram................................................................................................... 348
10.2 Functional Description.................................................................................................... 349
10.2.1 Initialization and Configuration................................................................................ 349
10.3 WATCHDOG Registers .................................................................................................. 350
10.3.1 WDTLOAD Register (offset = 0h) [reset = FFFFFFFFh] .................................................. 351
10.3.2 WDTVALUE Register (offset = 4h) [reset = FFFFFFFFh]................................................. 352
10.3.3 WDTCTL Register (offset = 8h) [reset = 80000000h]...................................................... 353
10.3.4 WDTICR Register (offset = Ch) [reset = 0h] ................................................................ 354
10.3.5 WDTRIS Register (offset = 10h) [reset = 0h] ............................................................... 355
10.3.6 WDTTEST Register (offset = 418h) [reset = 0h] ........................................................... 356
10.3.7 WDTLOCK Register (offset = C00h) [reset = 0h]........................................................... 357
10.4 MCU Watchdog Controller Usage Caveats ........................................................................... 358
10.4.1 System Watchdog .............................................................................................. 358
10.4.2 System Watchdog Recovery Sequence ..................................................................... 360
11 SD Host Controller Interface .............................................................................................. 361
11.1 Overview ................................................................................................................... 362
11.2 SD Host Features......................................................................................................... 362
11.3 1-Bit SD Interface......................................................................................................... 362
11.3.1 Clock and Reset Management................................................................................ 364
11.4 Initialization and Configuration Using Peripheral APIs............................................................... 364
11.4.1 Basic Initialization and Configuration......................................................................... 364
11.4.2 Sending Command ............................................................................................. 365
11.4.3 Card Detection and Initialization.............................................................................. 366
11.4.4 Block Read ...................................................................................................... 368
11.4.5 Block Write ...................................................................................................... 369
11.5 Performance and Testing................................................................................................ 369
11.6 Peripheral Library APIs .................................................................................................. 370
11.7 SD-HOST Registers...................................................................................................... 375
11.7.1 MMCHS_CSRE Register (Offset = 124h) [reset = 0h]..................................................... 376
11.7.2 MMCHS_CON Register (Offset = 12Ch) [reset = 0h]...................................................... 377
11.7.3 MMCHS_BLK Register (Offset = 204h) [reset = 0h] ....................................................... 379
11.7.4 MMCHS_ARG Register (Offset = 208h) [reset = 0h] ...................................................... 380
11.7.5 MMCHS_CMD Register (Offset = 20Ch) [reset = 0h]...................................................... 381
11.7.6 MMCHS_RSP10 Register (Offset = 210h) [reset = 0h].................................................... 383
11.7.7 MMCHS_RSP32 Register (Offset = 214h) [reset = 0h].................................................... 384
11.7.8 MMCHS_RSP54 Register (Offset = 218h) [reset = 0h].................................................... 385
11.7.9 MMCHS_RSP76 Register (Offset = 21Ch) [reset = 0h] ................................................... 386
11.7.10 MMCHS_DATA Register (Offset = 220h) [reset = 0h] ................................................... 387
11.7.11 MMCHS_PSTATE Register (Offset = 224h) [reset = 0h] ................................................ 388
11.7.12 MMCHS_HCTL Register (Offset = 228h) [reset = 0h].................................................... 390
11.7.13 MMCHS_SYSCTL Register (Offset = 22Ch) [reset = 0h]................................................ 391
11.7.14 MMCHS_STAT Register (Offset = 230h) [reset = 0h].................................................... 393
11.7.15 MMCHS_IE Register (Offset = 234h) [reset = 0h] ........................................................ 397
11.7.16 MMCHS_ISE Register (Offset = 238h) [reset = 0h] ...................................................... 399