Texas Instruments CC3235 SimpleLink Series - Page 5

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5
SWRU543–January 2019
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Contents
8.2.5 Interrupts.......................................................................................................... 280
8.2.6 DMA Requests ................................................................................................... 280
8.2.7 Reset .............................................................................................................. 281
8.3 Initialization and Configuration .......................................................................................... 281
8.3.1 Basic Initialization................................................................................................ 281
8.3.2 Master Mode Operation Without Interrupt (Polling) ......................................................... 281
8.3.3 Slave Mode Operation With Interrupt ......................................................................... 282
8.3.4 Generic Interrupt Handler Implementation ................................................................... 282
8.4 Access to Data Registers................................................................................................ 282
8.5 Module Initialization....................................................................................................... 283
8.5.1 Common Transfer Sequence................................................................................... 283
8.5.2 End-of-Transfer Sequences .................................................................................... 284
8.5.3 FIFO Mode........................................................................................................ 285
8.6 SPI Registers.............................................................................................................. 290
8.6.1 SPI_SYSCONFIG Register (offset = 10h) [reset = 0h] ..................................................... 291
8.6.2 SPI_SYSSTATUS Register (offset = 114h) [reset = 0h].................................................... 292
8.6.3 SPI_IRQSTATUS Register (offset = 118h) [reset = 0h] .................................................... 293
8.6.4 SPI_IRQENABLE Register (offset = 11Ch) [reset = 0h].................................................... 295
8.6.5 SPI_MODULCTRL Register (offset = 128h) [reset = 4h]................................................... 296
8.6.6 SPI_CHCONF Register (offset = 12Ch) [reset = 60000h].................................................. 297
8.6.7 SPI_CHSTAT Register (offset = 130h) [reset = 0h]......................................................... 300
8.6.8 SPI_CHCTRL Register (offset = 134h) [reset = 0h]......................................................... 301
8.6.9 SPI_TX Register (offset = 138h) [reset = 0h] ................................................................ 302
8.6.10 SPI_RX Register (offset = 13Ch) [reset = 0h] .............................................................. 303
8.6.11 SPI_XFERLEVEL Register (offset = 17Ch) [reset = 0h]................................................... 304
9 General-Purpose Timers.................................................................................................... 305
9.1 Overview ................................................................................................................... 306
9.2 Block Diagram............................................................................................................. 306
9.3 Functional Description.................................................................................................... 307
9.3.1 GPTM Reset Conditions ........................................................................................ 308
9.3.2 Timer Modes ..................................................................................................... 309
9.3.3 DMA Operation................................................................................................... 314
9.3.4 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................... 314
9.4 Initialization and Configuration .......................................................................................... 315
9.4.1 One-Shot and Periodic Timer Mode........................................................................... 315
9.4.2 Input Edge-Count Mode......................................................................................... 315
9.4.3 Input Edge-Time Mode.......................................................................................... 316
9.4.4 PWM Mode ....................................................................................................... 316
9.5 Timer Registers ........................................................................................................... 317
9.5.1 GPTMCFG Register (offset = 0h) [reset = 0h] ............................................................... 318
9.5.2 GPTMTAMR Register (offset = 4h) [reset = 0h] ............................................................. 319
9.5.3 GPTMTBMR Register (offset = 8h) [reset = 0h] ............................................................. 321
9.5.4 GPTMCTL Register (offset = Ch) [reset = 0h] ............................................................... 323
9.5.5 GPTMIMR Register (offset = 18h) [reset = 0h] .............................................................. 325
9.5.6 GPTMRIS Register (offset = 1Ch) [reset = 0h] .............................................................. 327
9.5.7 GPTMMIS Register (offset = 20h) [reset = 0h] .............................................................. 329
9.5.8 GPTMICR Register (offset = 24h) [reset = 0h]............................................................... 331
9.5.9 GPTMTAILR Register (offset = 28h) [reset = FFFFFFFFh]................................................ 333
9.5.10 GPTMTBILR Register (offset = 2Ch) [reset = FFFFh] ..................................................... 334
9.5.11 GPTMTAMATCHR Register (offset = 30h) [reset = FFFFFFFFh] ....................................... 335
9.5.12 GPTMTBMATCHR Register (offset = 34h) [reset = FFFFh] .............................................. 336
9.5.13 GPTMTAPR Register (offset = 38h) [reset = 0h] ........................................................... 337
9.5.14 GPTMTBPR Register (offset = 3Ch) [reset = 0h]........................................................... 338