Texas Instruments CC3235 SimpleLink Series - Page 4

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4
SWRU543–January 2019
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Contents
6.3.9 UARTIM Register (Offset = 38h) [reset = 0h] ................................................................ 194
6.3.10 UARTRIS Register (Offset = 3Ch) [reset = 0h] ............................................................. 196
6.3.11 UARTMIS Register (Offset = 40h) [reset = 0h] ............................................................. 198
6.3.12 UARTICR Register (Offset = 44h) [reset = 0h] ............................................................. 200
6.3.13 UARTDMACTL Register (Offset = 48h) [reset = 0h]....................................................... 202
7 Inter-Integrated Circuit (I
2
C) Interface .................................................................................. 203
7.1 Overview ................................................................................................................... 204
7.1.1 Block Diagram.................................................................................................... 204
7.1.2 Signal Description ............................................................................................... 205
7.2 Functional Description.................................................................................................... 206
7.2.1 I2C Bus Functional Overview .................................................................................. 206
7.2.2 Supported Speed Modes ....................................................................................... 210
7.2.3 Interrupts.......................................................................................................... 211
7.2.4 Loopback Operation............................................................................................. 211
7.2.5 FIFO and µDMA Operation..................................................................................... 211
7.2.6 Command Sequence Flow Charts............................................................................. 213
7.2.7 Initialization and Configuration ................................................................................. 221
7.3 I2C Registers.............................................................................................................. 222
7.3.1 I2CMSA Register (Offset = 0h) [reset = 0h].................................................................. 223
7.3.2 I2CMCS Register (Offset = 4h) [reset = 20h] ................................................................ 224
7.3.3 I2CMDR Register (Offset = 8h) [reset = 0h].................................................................. 229
7.3.4 I2CMTPR Register (Offset = Ch) [reset = 1h]................................................................ 230
7.3.5 I2CMIMR Register (Offset = 10h) [reset = 0h] ............................................................... 231
7.3.6 I2CMRIS Register (Offset = 14h) [reset = 0h] ............................................................... 233
7.3.7 I2CMMIS Register (Offset = 18h) [reset = 0h] ............................................................... 235
7.3.8 I2CMICR Register (Offset = 1Ch) [reset = 0h]............................................................... 237
7.3.9 I2CMCR Register (Offset = 20h) [reset = 0h] ................................................................ 239
7.3.10 I2CMCLKOCNT Register (Offset = 24h) [reset = 0h] ...................................................... 240
7.3.11 I2CMBMON Register (Offset = 2Ch) [reset = 3h] .......................................................... 241
7.3.12 I2CMBLEN Register (Offset = 30h) [reset = 0h]............................................................ 242
7.3.13 I2CMBCNT Register (Offset = 34h) [reset = 0h]............................................................ 243
7.3.14 I2CSOAR Register (Offset = 800h) [reset = 0h] ............................................................ 244
7.3.15 I2CSCSR Register (Offset = 804h) [reset = 0h] ............................................................ 245
7.3.16 I2CSDR Register (Offset = 808h) [reset = 0h].............................................................. 247
7.3.17 I2CSIMR Register (Offset = 80Ch) [reset = 0h] ............................................................ 248
7.3.18 I2CSRIS Register (Offset = 810h) [reset = 0h] ............................................................. 250
7.3.19 I2CSMIS Register (Offset = 814h) [reset = 0h] ............................................................. 252
7.3.20 I2CSICR Register (Offset = 818h) [reset = 0h] ............................................................. 254
7.3.21 I2CSOAR2 Register (Offset = 81Ch) [reset = 0h] .......................................................... 256
7.3.22 I2CSACKCTL Register (Offset = 820h) [reset = 0h] ....................................................... 257
7.3.23 I2CFIFODATA Register (Offset = F00h) [reset = 0h] ...................................................... 258
7.3.24 I2CFIFOCTL Register (Offset = F04h) [reset = 00040004h].............................................. 259
7.3.25 I2CFIFOSTATUS Register (Offset = F08h) [reset = 00010005h] ........................................ 261
7.3.26 I2CPP Register (Offset = FC0h) [reset = 1h] ............................................................... 262
7.3.27 I2CPC Register (Offset = FC4h) [reset = 1h] ............................................................... 263
8 SPI (Serial Peripheral Interface).......................................................................................... 264
8.1 Overview ................................................................................................................... 265
8.1.1 Features........................................................................................................... 265
8.2 Functional Description.................................................................................................... 266
8.2.1 SPI ................................................................................................................ 266
8.2.2 SPI Transmission ................................................................................................ 266
8.2.3 Master Mode ..................................................................................................... 270
8.2.4 Slave Mode....................................................................................................... 277