Texas Instruments CC3235 SimpleLink Series - Page 3

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3
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Contents
3.3.1 Cortex Registers................................................................................................... 83
4 Direct Memory Access (DMA)............................................................................................. 117
4.1 Overview ................................................................................................................... 118
4.2 Functional Description.................................................................................................... 118
4.2.1 Channel Assignment ............................................................................................ 119
4.2.2 Priority............................................................................................................. 120
4.2.3 Arbitration Size................................................................................................... 120
4.2.4 Channel Configuration .......................................................................................... 120
4.2.5 Transfer Mode.................................................................................................... 122
4.2.6 Transfer Size and Increment ................................................................................... 125
4.2.7 Peripheral Interface.............................................................................................. 126
4.2.8 Interrupts and Errors ............................................................................................ 127
4.3 Register Description...................................................................................................... 127
4.3.1 DMA Register Map .............................................................................................. 127
4.3.2 µDMA Channel Control Structure.............................................................................. 128
4.3.3 DMA Registers ................................................................................................... 128
4.3.4 DMA_(OFFSET_FROM_DMA_BASE_ADDRESS) Registers............................................. 132
5 General-Purpose Input/Outputs (GPIOs).............................................................................. 156
5.1 Overview ................................................................................................................... 157
5.2 Functional Description.................................................................................................... 157
5.2.1 Data Control ...................................................................................................... 158
5.3 Interrupt Control........................................................................................................... 159
5.3.1 µDMA Trigger Source ........................................................................................... 159
5.4 Initialization and Configuration .......................................................................................... 159
5.5 GPIO Registers ........................................................................................................... 161
5.5.1 GPIODATA Register (offset = 0h) [reset = 0h]............................................................... 162
5.5.2 GPIODIR Register (offset = 400h) [reset = 0h] .............................................................. 163
5.5.3 GPIOIS Register (offset = 404h) [reset = 0h] ................................................................ 164
5.5.4 GPIOIBE Register (offset = 408h) [reset = 0h] .............................................................. 165
5.5.5 GPIOIEV Register (offset = 40Ch) [reset = 0h].............................................................. 166
5.5.6 GPIOIM Register (offset = 410h) [reset = 0h]................................................................ 167
5.5.7 GPIORIS Register (offset = 414h) [reset = 0h] .............................................................. 168
5.5.8 GPIOMIS Register (offset = 418h) [reset = 0h].............................................................. 169
5.5.9 GPIOICR Register (offset = 41Ch) [reset = 0h].............................................................. 170
5.5.10 GPIO_TRIG_EN Register ..................................................................................... 171
6 Universal Asynchronous Receivers/Transmitters (UARTs) .................................................... 173
6.1 Overview ................................................................................................................... 174
6.1.1 Block Diagram.................................................................................................... 174
6.2 Functional Description.................................................................................................... 175
6.2.1 Transmit and Receive Logic.................................................................................... 175
6.2.2 Baud-Rate Generation .......................................................................................... 176
6.2.3 Data Transmission............................................................................................... 176
6.2.4 Initialization and Configuration ................................................................................. 179
6.3 UART Registers........................................................................................................... 181
6.3.1 UARTDR Register (Offset = 0h) [reset = 0h]................................................................. 182
6.3.2 UARTRSR_UARTECR Register (Offset = 4h) [reset = 0h] ................................................ 183
6.3.3 UARTFR Register (Offset = 18h) [reset = 90h] .............................................................. 185
6.3.4 UARTIBRD Register (Offset = 24h) [reset = 0h]............................................................. 187
6.3.5 UARTFBRD Register (Offset = 28h) [reset = 0h]............................................................ 188
6.3.6 UARTLCRH Register (Offset = 2Ch) [reset = 0h] ........................................................... 189
6.3.7 UARTCTL Register (Offset = 30h) [reset = 300h] ........................................................... 191
6.3.8 UARTIFLS Register (Offset = 34h) [reset = 12h]............................................................ 193