Texas Instruments CC3235 SimpleLink Series - Page 2

2
SWRU543–January 2019
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Copyright © 2019, Texas Instruments Incorporated
Contents
Contents
Preface....................................................................................................................................... 36
1 Architecture Overview......................................................................................................... 39
1.1 Introduction.................................................................................................................. 40
1.2 Architecture Overview ..................................................................................................... 41
1.3 Functional Overview ....................................................................................................... 42
1.3.1 Processor Core.................................................................................................... 42
1.3.2 Memory ............................................................................................................. 43
1.3.3 Micro-Direct Memory Access Controller (µDMA).............................................................. 44
1.3.4 General-Purpose Timer (GPT) .................................................................................. 45
1.3.5 Watchdog Timer (WDT) .......................................................................................... 45
1.3.6 Multichannel Audio Serial Port (McASP)....................................................................... 45
1.3.7 Serial Peripheral Interface (SPI)................................................................................. 46
1.3.8 Inter-Integrated Circuit (I2C) Interface ......................................................................... 46
1.3.9 Universal Asynchronous Receiver/Transmitter (UART)...................................................... 46
1.3.10 General-Purpose Input/Output (GPIO) ........................................................................ 47
1.3.11 Analog-to-Digital Converter (ADC)............................................................................. 47
1.3.12 SD Card Host .................................................................................................... 47
1.3.13 Parallel Camera Interface ...................................................................................... 48
1.3.14 Debug Interface .................................................................................................. 48
1.3.15 Hardware Cryptography Accelerator........................................................................... 48
1.3.16 Clock, Reset, and Power Management ....................................................................... 48
1.3.17 SimpleLink™ Subsystem........................................................................................ 49
1.3.18 I/O Pads and Pin Multiplexing .................................................................................. 49
2 Cortex
®
-M4 Processor......................................................................................................... 50
2.1 Overview..................................................................................................................... 51
2.1.1 Block Diagram ..................................................................................................... 52
2.1.2 System-Level Interface ........................................................................................... 52
2.1.3 Integrated Configurable Debug.................................................................................. 52
2.1.4 Trace Port Interface Unit (TPIU) ................................................................................ 53
2.1.5 Cortex
®
-M4 System Component Details ....................................................................... 53
2.2 Functional Description ..................................................................................................... 54
2.2.1 Programming Model .............................................................................................. 54
2.2.2 Register Description .............................................................................................. 55
2.2.3 Memory Model..................................................................................................... 58
2.2.4 Exception Model................................................................................................... 62
2.2.5 Fault Handling ..................................................................................................... 68
2.2.6 Power Management............................................................................................... 71
2.2.7 Instruction Set Summary ......................................................................................... 73
3 Cortex
®
-M4 Peripherals ....................................................................................................... 77
3.1 Overview..................................................................................................................... 78
3.2 Functional Description ..................................................................................................... 78
3.2.1 System Timer (SysTick) .......................................................................................... 78
3.2.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 79
3.2.3 System Control Block (SCB)..................................................................................... 80
3.3 Register Map................................................................................................................ 80