Texas Instruments CC3235 SimpleLink Series - Page 9

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9
SWRU543–January 2019
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Contents
15.3.10 Slow Clock Counter........................................................................................... 528
15.4 Peripheral Macros ........................................................................................................ 529
15.5 Power Management Framework........................................................................................ 529
15.6 PRCM Registers .......................................................................................................... 529
15.6.1 CAMCLKCFG Register (offset = 0h) [reset = 0h]........................................................... 531
15.6.2 CAMCLKEN Register (offset = 4h) [reset = 0h] ............................................................ 532
15.6.3 CAMSWRST Register (offset = 8h) [reset = 0h]............................................................ 533
15.6.4 MCASPCLKEN Register (offset = 14h) [reset = 0h] ....................................................... 534
15.6.5 MCASPSWRST Register (offset = 18h) [reset = 0h]....................................................... 535
15.6.6 SDIOMCLKCFG Register (offset = 20h) [reset = 0h] ...................................................... 536
15.6.7 SDIOMCLKEN Register (offset = 24h) [reset = 0h] ........................................................ 537
15.6.8 SDIOMSWRST Register (offset = 28h) [reset = 0h] ....................................................... 538
15.6.9 APSPICLKCFG Register (offset = 2Ch) [reset = 0h]....................................................... 539
15.6.10 APSPICLKEN Register (offset = 30h) [reset = 0h] ....................................................... 540
15.6.11 APSPISWRST Register (offset = 34h) [reset = 0h]....................................................... 541
15.6.12 DMACLKEN Register (offset = 48h) [reset = 0h] ......................................................... 542
15.6.13 DMASWRST Register (offset = 4Ch) [reset = 0h] ........................................................ 543
15.6.14 GPIO0CLKEN Register (offset = 50h) [reset = 0h] ....................................................... 544
15.6.15 GPIO0SWRST Register (offset = 54h) [reset = 0h] ...................................................... 545
15.6.16 GPIO1CLKEN Register (offset = 58h) [reset = 0h] ....................................................... 546
15.6.17 GPIO1SWRST Register (offset = 5Ch) [reset = 0h] ...................................................... 547
15.6.18 GPIO2CLKEN Register (offset = 60h) [reset = 0h] ....................................................... 548
15.6.19 GPIO2SWRST Register (offset = 64h) [reset = 0h] ...................................................... 549
15.6.20 GPIO3CLKEN Register (offset = 68h) [reset = 0h] ....................................................... 550
15.6.21 GPIO3SWRST Register (offset = 6Ch) [reset = 0h] ...................................................... 551
15.6.22 GPIO4CLKEN Register (offset = 70h) [reset = 0h] ....................................................... 552
15.6.23 GPIO4SWRST Register (offset = 74h) [reset = 0h] ...................................................... 553
15.6.24 WDTCLKEN Register (offset = 78h) [reset = 0h] ......................................................... 554
15.6.25 WDTSWRST Register (offset = 7Ch) [reset = 0h] ........................................................ 555
15.6.26 UART0CLKEN Register (offset = 80h) [reset = 0h]....................................................... 556
15.6.27 UART0SWRST Register (offset = 84h) [reset = 0h]...................................................... 557
15.6.28 UART1CLKEN Register (offset = 88h) [reset = 0h]....................................................... 558
15.6.29 UART1SWRST Register (offset = 8Ch) [reset = 0h] ..................................................... 559
15.6.30 GPT0CLKCFG Register (offset = 90h) [reset = 0h] ...................................................... 560
15.6.31 GPT0SWRST Register (offset = 94h) [reset = 0h]........................................................ 561
15.6.32 GPT1CLKEN Register (offset = 98h) [reset = 0h] ........................................................ 562
15.6.33 GPT1SWRST Register (offset = 9Ch) [reset = 0h] ....................................................... 563
15.6.34 GPT2CLKEN Register (offset = A0h) [reset = 0h] ........................................................ 564
15.6.35 GPT2SWRST Register (offset = A4h) [reset = 0h] ....................................................... 565
15.6.36 GPT3CLKEN Register (offset = A8h) [reset = 0h] ........................................................ 566
15.6.37 GPT3SWRST Register (offset = ACh) [reset = 0h]....................................................... 567
15.6.38 MCASPCLKCFG0 Register (offset = B0h) [reset = A0000h]............................................ 568
15.6.39 MCASPCLKCFG1 Register (offset = B4h) [reset = 0h] .................................................. 569
15.6.40 I2CLCKEN Register (offset = D8h) [reset = 0h]........................................................... 570
15.6.41 I2CSWRST Register (offset = DCh) [reset = 0h].......................................................... 571
15.6.42 LPDSREQ Register (offset = E4h) [reset = 0h] ........................................................... 572
15.6.43 TURBOREQ Register (offset = ECh) [reset = 0h] ........................................................ 573
15.6.44 DSLPWAKECFG Register (offset = 108h) [reset = 0h] .................................................. 574
15.6.45 DSLPTIMRCFG Register (offset = 10Ch) [reset = 0h] ................................................... 575
15.6.46 SLPWAKEEN Register (offset = 110h) [reset = 0h] ...................................................... 576
15.6.47 SLPTMRCFG Register (offset = 114h) [reset = 0h] ...................................................... 577
15.6.48 WAKENWP Register (offset = 118h) [reset = 0h]......................................................... 578
15.6.49 RCM_IS Register (offset = 120h) [reset = 0h]............................................................. 579