Texas Instruments CC3235 SimpleLink Series - Page 10

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10
SWRU543–January 2019
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Contents
15.6.50 RCM_IEN Register (offset = 124h) [reset = 0h]........................................................... 580
16 I/O Pads and Pin Multiplexing............................................................................................. 581
16.1 Overview ................................................................................................................... 582
16.2 I/O Pad Electrical Specifications........................................................................................ 583
16.3 Analog and Digital Pin Multiplexing .................................................................................... 584
16.4 Special Analog/Digital Pins.............................................................................................. 584
16.4.1 Pins 45 and 52 .................................................................................................. 584
16.4.2 Pins 29 and 30 .................................................................................................. 584
16.4.3 Pins 57, 58, 59, and 60 ........................................................................................ 584
16.5 Analog Mux Control Registers .......................................................................................... 587
16.6 Pins Available for Applications.......................................................................................... 589
16.7 Functional Pin Mux Configurations ..................................................................................... 591
16.8 Pin Mapping Recommendations........................................................................................ 603
16.8.1 Pad Configuration Registers for Application Pins .......................................................... 604
16.8.2 PAD Behavior During Reset and Hibernate................................................................. 605
16.8.3 Control Architecture ............................................................................................ 606
16.8.4 CC32xx Pin-mux Examples ................................................................................... 606
16.8.5 Wake on Pad.................................................................................................... 609
16.8.6 Sense on Power ................................................................................................ 610
17 Advance Encryption Standard Accelerator (AES) ................................................................. 611
17.1 AES Overview............................................................................................................. 612
17.2 AES Functional Description ............................................................................................. 612
17.2.1 AES Block Diagram ............................................................................................ 612
17.2.2 AES Algorithm................................................................................................... 615
17.2.3 AES Operating Modes ......................................................................................... 616
17.2.4 Hardware Requests ............................................................................................ 626
17.3 AES Module Programming Guide ...................................................................................... 627
17.3.1 AES Low-Level Programming Models ....................................................................... 627
17.4 AES Registers............................................................................................................. 632
17.4.1 AES_KEY2_6 Register (Offset = 0h) [reset = 0h] .......................................................... 633
17.4.2 AES_KEY2_7 Register (Offset = 4h) [reset = 0h] .......................................................... 633
17.4.3 AES_KEY2_4 Register (Offset = 8h) [reset = 0h] .......................................................... 634
17.4.4 AES_KEY2_5 Register (Offset = Ch) [reset = 0h].......................................................... 634
17.4.5 AES_KEY2_2 Register (Offset = 10h) [reset = 0h]......................................................... 635
17.4.6 AES_KEY2_3 Register (Offset = 14h) [reset = 0h]......................................................... 635
17.4.7 AES_KEY2_0 Register (Offset = 18h) [reset = 0h]......................................................... 636
17.4.8 AES_KEY2_1 Register (Offset = 1Ch) [reset = 0h] ........................................................ 636
17.4.9 AES_KEY1_6 Register (Offset = 20h) [reset = 0h]......................................................... 637
17.4.10 AES_KEY1_7 Register (Offset = 24h) [reset = 0h] ....................................................... 637
17.4.11 AES_KEY1_4 Register (Offset = 28h) [reset = 0h] ....................................................... 638
17.4.12 AES_KEY1_5 Register (Offset = 2Ch) [reset = 0h]....................................................... 638
17.4.13 AES_KEY1_2 Register (Offset = 30h) [reset = 0h] ....................................................... 639
17.4.14 AES_KEY1_3 Register (Offset = 34h) [reset = 0h] ....................................................... 639
17.4.15 AES_KEY1_0 Register (Offset = 38h) [reset = 0h] ....................................................... 640
17.4.16 AES_KEY1_1 Register (Offset = 3Ch) [reset = 0h]....................................................... 640
17.4.17 AES_IV_IN_0 Register (Offset = 40h) [reset = 0h] ....................................................... 641
17.4.18 AES_IV_IN_1 Register (Offset = 44h) [reset = 0h] ....................................................... 641
17.4.19 AES_IV_IN_2 Register (Offset = 48h) [reset = 0h] ....................................................... 642
17.4.20 AES_IV_IN_3 Register (Offset = 4Ch) [reset = 0h]....................................................... 642
17.4.21 AES_CTRL Register (Offset = 50h) [reset = X] ........................................................... 643
17.4.22 AES_C_LENGTH_0 Register (Offset = 54h) [reset = 0h]................................................ 646
17.4.23 AES_C_LENGTH_1 Register (Offset = 58h) [reset = X]................................................. 647
17.4.24 AES_AUTH_LENGTH Register (Offset = 5Ch) [reset = 0h]............................................. 648