Texas Instruments CC3235 SimpleLink Series - Page 11

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11
SWRU543–January 2019
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Contents
17.4.25 AES_DATA_IN_0 Register (Offset = 60h) [reset = 0h]................................................... 649
17.4.26 AES_DATA_IN_1 Register (Offset = 64h) [reset = 0h]................................................... 649
17.4.27 AES_DATA_IN_2 Register (Offset = 68h) [reset = 0h]................................................... 650
17.4.28 AES_DATA_IN_3 Register (Offset = 6Ch) [reset = 0h] .................................................. 650
17.4.29 AES_TAG_OUT_0 Register (Offset = 70h) [reset = 0h] ................................................. 651
17.4.30 AES_TAG_OUT_1 Register (Offset = 74h) [reset = 0h] ................................................. 651
17.4.31 AES_TAG_OUT_2 Register (Offset = 78h) [reset = 0h] ................................................. 652
17.4.32 AES_TAG_OUT_3 Register (Offset = 7Ch) [reset = 0h]................................................. 652
17.4.33 AES_REVISION Register (Offset = 80h) [reset = X] ..................................................... 653
17.4.34 AES_SYSCONFIG Register (Offset = 84h) [reset = X] .................................................. 655
17.4.35 AES_IRQSTATUS Register (Offset = 8Ch) [reset = X] .................................................. 656
17.4.36 AES_IRQENABLE Register (Offset = 90h) [reset = X]................................................... 657
17.4.37 CRYPTOCLKEN Register (Offset = B8h) [reset = X]..................................................... 658
17.4.38 DTHE_AES_IM Register (Offset = 820h) [reset = X]..................................................... 659
17.4.39 DTHE_AES_RIS Register (Offset = 824h) [reset = X] ................................................... 660
17.4.40 DTHE_AES_MIS Register (Offset = 828h) [reset = X] ................................................... 661
17.4.41 DTHE_AES_IC Register (Offset = 82Ch) [reset = X]..................................................... 662
18 Data Encryption Standard Accelerator (DES) ....................................................................... 663
18.1 DES Functional Description ............................................................................................. 664
18.2 DES Block Diagram ...................................................................................................... 664
18.2.1 µDMA Control ................................................................................................... 665
18.2.2 Interrupt Control................................................................................................. 665
18.2.3 Register Interface............................................................................................... 666
18.2.4 DES Enginer..................................................................................................... 666
18.3 DES-Supported Modes of Operation................................................................................... 666
18.3.1 ECB Feedback Mode .......................................................................................... 666
18.4 DES Module Programming Guide – Low-Level Programming Models ............................................ 668
18.4.1 Surrounding Modules Global Initialization ................................................................... 668
18.4.2 Operational Modes Configuration ............................................................................ 669
18.4.3 DES Events Servicing.......................................................................................... 671
18.5 DES Registers............................................................................................................. 673
18.5.1 DTHE_DES_IM Register (Offset = 830h) [reset = Dh]..................................................... 674
18.5.2 DTHE_DES_RIS Register (Offset = 834h) [reset = 0h] ................................................... 675
18.5.3 DTHE_DES_MIS Register (Offset = 838h) [reset = 0h] ................................................... 676
18.5.4 DTHE_DES_IC Register (Offset = 83Ch) [reset = 0h]..................................................... 677
18.5.5 DES_KEY3_L Register (Offset = 1000h) [reset = 0h] ..................................................... 678
18.5.6 DES_KEY3_H Register (Offset = 1004h) [reset = 0h]..................................................... 679
18.5.7 DES_KEY2_L Register (Offset = 1008h) [reset = 0h] ..................................................... 680
18.5.8 DES_KEY2_H Register (Offset = 100Ch) [reset = 0h] .................................................... 681
18.5.9 DES_KEY1_L Register (Offset = 1010h) [reset = 0h] ..................................................... 682
18.5.10 DES_KEY1_H Register (Offset = 1014h) [reset = 0h] ................................................... 683
18.5.11 DES_IV_L Register (Offset = 1018h) [reset = 0h] ........................................................ 684
18.5.12 DES_IV_H Register (Offset = 101Ch) [reset = 0h] ....................................................... 685
18.5.13 DES_CTRL Register (Offset = 1020h) [reset = 80000000h] ............................................ 686
18.5.14 DES_LENGTH Register (Offset = 1024h) [reset = 0h]................................................... 687
18.5.15 DES_DATA_L Register (Offset = 1028h) [reset = 0h].................................................... 688
18.5.16 DES_DATA_H Register (Offset = 102Ch) [reset = 0h]................................................... 689
18.5.17 DES_SYSCONFIG Register (Offset = 1034h) [reset = 0h].............................................. 690
18.5.18 DES_IRQSTATUS Register (Offset = 103Ch) [reset = 0h].............................................. 691
18.5.19 DES_IRQENABLE Register (Offset = 1040h) [reset = 0h] .............................................. 692
19 SHA/MD5 Accelerator........................................................................................................ 693
19.1 SHA/MD5 Functional Description....................................................................................... 694
19.1.1 SHA/MD5 Block Diagram...................................................................................... 694