Analog Devices SHARC ADSP-21368 - Page 882

Index
I-26 ADSP-21368 SHARC Processor Hardware Reference
shared memory
See also external port
asynchronous access mode, 3-81
bus arbitration, 3-79
code select (CSEL) bit, 3-82
force sync of shared memory bus
(FSYNC) bit, A-8
interface status, 3-93
memory select (MSx
) pins, 3-83
pins, 3-81
rotating priority bus arbitration select
(RPBA) pin, 3-81
system design diagram, 3-79
write (WR
) pin, 3-83
short-circuit condition, PWM, 8-6
signal naming convention, 4-9
signal routing unit external miscellaneous
(MISCAx) registers, 13-13
signal routing unit. See SRU, DAI, DPI
signals
acknowledge (ACK), 3-2, 3-19, 3-21
AMI, listed, 3-20
bidirectional, 4-13
BLK_START, 9-11
bus grant HBG
, 3-89
bus request BRx
, 3-79, 3-85, 3-89, 3-92
CLKIN, 14-20
clock (serial port), 5-13
external memory, 3-16
falling edge, 4-70
frame sync (serial port), 5-13
groups in signal routing units, 4-8
input pins in DAI/DPI, 4-12
interrupt generation from SRU, 4-69
memory read RD
, 3-21
memory select MSx
, 3-89
miscellaneous for general-purpose I/O
SRU, 4-65
mnemonics in signal routing units, 4-9
output pins in DAI/DPI, 4-11
signals (continued)
pin buffers, 4-10
pin output routing, 4-12
pin routing, 4-10
read, 3-25
responding to, 4-71
rising edge, 4-70
rotating priority bus select (RPBA), 3-81
routing in SRU, 4-18
sensitivity in serial ports, 5-9
serial port, 5-5 to 5-10
signal routing group assignments, 4-8
slave select (SPI), 2-43
SPDIF bi-phase encoded data input
(DIR_I), 9-18
SPDIF bi-phase output (DIT_O), 9-11
SPDIF clock (DIT_CLK_I), 9-10
SPDIF external sync
(DIT_EXT_SYNCEN), 9-11
SPDIF frame sync (DIT_FS_I), 9-10
SPDIF frame sync feed back out
(DIR_LRCLK_O), 9-19
SPDIF frame sync reference out
(DIR_LRCLK_REF_O), 9-19
SPDIF oversampling clock
(DIT_HFCLK_I), 9-11
SPDIF PLL clock (DIR_PLLCLK_I),
9-18
SPDIF serial data (DIT_DAT_I), 9-10
SPI clock (SPICLK), 6-2
SPI device select (SPIDS
), 6-2
structure in signal routing units, 4-8
write WR
, 3-21
single-channel, double-frequencey mode
(S/PDIF), 9-8
sizes in SDRAM, page, 3-34
slave mode DMA operations (SPI), 6-19
slave mode operation, configure for, 6-11
SLEN (select word length) bits, 5-17, 5-22,
5-29, 5-62