Analog Devices SHARC ADSP-21368 - Page 881

ADSP-21368 SHARC Processor Hardware Reference I-25
Index
SDRAM controller (continued)
definitions, 3-31 to 3-36
disable, 3-40
external data path width, setting, 3-43
external memory access timing, 3-36
forcing auto refresh, 3-45
forcing precharge, 3-45
internal bank, 3-33
mode register, 3-33
optimal data throughput, 3-74 to 3-77
page size, 3-34
power-up sequence, A-23, A-24
power-up sequence start, 3-43
precharge (SDTRP) bit, 3-37
RAS to CAS delay (SDTRCD) bit, 3-37
read/write command, 3-67
refresh rate (SDRRC) register, 3-49
row address and page size, 3-34
row address width, setting, 3-48
self-refresh, 3-34
setting bank column address width, 3-42,
A-25
setting CAS latency, 3-40
status (SDSTAT) register, 3-49
stop burst, 3-32
timing, 3-74
tMRD definition, 3-35
tRAS definition, 3-35
tRC definition, 3-36
tRCD definition, 3-35
tRFC definition, 3-36
tRP definition, 3-35
tRRD definition, 3-36
tWR definition, 3-35
tXSR definition, 3-36
uniprocessor system with multiple
SDRAM devices diagram, 3-46, 3-47
write before precharge (SDTWR) bit,
3-37
SDRAM controller commands
auto-refresh, 3-70
bank activate, 3-31, 3-65
burst stop, 3-32, 3-69
command pin states, 3-72
load mode register, 3-64
NOP/command inhibit, 3-72
precharge,
3-34
precharge all, 3-66
self-refresh, 3-70
single precharge, 3-66
stop command, burst, 3-32
SDRAM controller registers, A-21 to A-26
control (SDCTL), A-21 to A-25
control status (SDSTAT), A-26
refresh rate control (SDRRC), A-26
select (MSx
) pins, memory, 3-53
self-refresh mode, 3-34
semaphores, 3-92
SENDZ (send zeros) bit, 6-11, 6-37
serial clock (SPORTx_CLK) pins, 5-6
serial communications, 11-2
serial inputs, 7-3
serial modes, specifying, 7-5
serial port transmit 4 (SP4I) bit, B-9
serial word
endian select (LSBF) bit, 5-62
length select bits (SLENx) bits, 5-17,
5-62
setting CAS latency, 3-40
setting hold time cycles, 3-23
setting the internal serial clock and frame
sync rates, 5-21
setting up DMA on SPORT channels, 5-75
setting word length (SLEN) bits, 5-17,
5-22
setup time, inputs, 14-32
SFTx (user software interrupt) bits, B-18,
B-21, B-26