Analog Devices SHARC ADSP-21368 - Page 880

Index
I-24 ADSP-21368 SHARC Processor Hardware Reference
S/PDIF registers (continued)
extracted receiver frame sync output
(SPDIF_RX_FS_O), 9-18
extracted receiver sample clock output
(SPDIF_RX_CLK_O), 9-18
receive control (DIRCTL), 9-12
receiver status (DIRSTAT), A-94
receiver TDM output
(SPDIF_RX_TDMCLK_O), 9-19
right channel status for subframe A
(DIRCHANL), A-96
right channel status for subframe B
(DIRCHANR), A-96
right channel transmit status
(DITCHANR), 9-12
transmit control (DITCTL), 9-12, 9-17,
A-86
transmit status (DITCHANL) left
channel, 9-12
user bit buffer (DITUSRBITAx), 9-12
sampling clock period, UART, 11-6
sampling point, UART, 11-6
SB (UART set break) bit, 11-3, A-118
SCHEN_A and SCHEN_B (serial port
chaining enable) bit, 5-63, A-38
SDEN (serial port DMA enable) bit, 2-48,
5-63, A-38
SDRAM
buffered system, 3-46, 3-47
bus errors, 3-71
core address mapping, 3-52
errors, 3-77
page size, 3-34
refresh rate, 3-50
restrictions, 3-52
SDRAM bits
burst stop (NOBSTOP), A-25
CAS latency (SDCL), A-22
column address width (SDCAW), A-23
SDRAM bits (continued)
disable clock and control (DSDCTL),
A-22
external data path width (X16DE), A-24
force auto refresh (Force AR), A-24
force load mode register write (Force
LMR), A-24
force precharge (Force PC), A-24
optimization (SDROPT), A-27
optional refresh (SDORF), A-24
page size is 128 words (PGSZ 128), A-25
pipeline option with external register
buffer (SDBUF), A-24
power-up mode (SDPM),
A-23
power-up sequence start (SDPSS), A-23
predictive addressing (SDMODIFY),
A-27
RAS setting (SDTRAS), A-23
RDC setting (SDTRCD), A-24
refresh delay (RDIV), A-27
row address width (SDRAW), A-25
RP setting (SDTRP), A-23
self-refresh enable (SDSRF), A-23
WR setting (SDTWR), A-24
SDRAM controller, 3-30
address space, external memory, 3-52
addressing (16-bit), 3-55 to 3-57
addressing (32-bit), 3-53 to 3-54
bank activate, 3-36
burst disable, A-25
burst length definition, 3-32
burst type, 3-32
calculating refresh rate, 3-50
CAS latency, 3-32
CAS latency (SDCL) bit, 3-37
CBR (CAS before RAS), 3-33
clock frequencies, 3-37
configuring, 3-62
control (SDCTL) register, 3-39
data mask, 3-33