ADSP-21368 SHARC Processor Hardware Reference I-33
Index
STATPA (program memory data
breakpoint hit) bit, A-181
STATUS field, 11-10
strobe period, 13-13
strobe pulse, 13-13
strobe, PDAP output, 7-14
STROBEA (one shot frame sync A) bit,
13-13, A-159
STROBEB (one shot frame sync B) bit,
13-13, A-159
supervisory circuits, 14-27
support, technical or customer, xxxv
switching frequencies
determining, 14-29
switching from receive to transmit DMA
(SPI), 6-24
switching from transmit to receive DMA
(SPI), 6-23
synchronization with the external clock,
13-7
synchronizing frame sync output, 13-7
synchronous access mode, 3-81
synchronous access mode (external port),
3-22
SYSCTL (system control) register, A-5
SYSCTL register
bus lock request (BUSLK) bit, A-8
external port data pin mode select
(EPDATA) bits, A-8
force sync of shared memory bus
(FSYNC) bit, A-8
internal interrupt vector table (IIVT) bit,
A-6
internal memory data width (IMDWx)
bits, A-7
interrupt request enable (IRQxEN) bits,
A-7
memory select (MSEN) bit, A-8
pulse width modulation select (PWMx)
bits, A-8
SYSCTL register (continued)
rotating priority bus arbitration (RBPR)
bit, A-7
SRST (software reset) bit, A-6
timer (flag) expired mode
(TMREXPEN) bit, A-8
system control register. See SYSCTL
register
system design
baud rate, init value, 14-49
boot configuration (BOOT_CFGx)
pins, 14-38
bypass capacitors, 14-35
CLKIN pin, 14-13, 14-20
CLKOUT and CCLK clock generation,
14-30
clock distribution, 14-34
clock input, 14-20
conditioning input signals, 14-32
crosstalk, reducing, 14-34
decoupling capacitors, 14-35
designing for high frequency operation,
14-33
determining switching frequencies,
14-29
flags (FLAGx) pins, 14-8
FLAGx pins, 14-8
generators, reset, 14-28
ground plane, 14-34
hold time, inputs, 14-32
input setup and hold time, 14-32
input signal conditioning, 14-32
JTAG interface pins, 14-12
latchup, 14-32
latency, input synchronization, 14-8
pins, descriptions, 14-2
plane, ground, 14-34
PLL-based clocking, 14-13
power supply, monitor and reset
generator, 14-28