Analog Devices SHARC ADSP-21368 - Page 890

Index
I-34 ADSP-21368 SHARC Processor Hardware Reference
system design (continued)
recommendations and suggestions,
14-34
RESET
pin, 14-33
shared memory system diagram, 3-79
stalls, 14-54
switching frequencies, 14-29
timing specifications, 14-28
system status (SYSTAT) register, A-9
T
TCB chain loading, 2-15, 2-16
TCK (test clock) pin, 14-12
TDI (test data input) pin, 14-12
TDM mode, time division multiplexed,
9-19
TDO (test data output) pin, 14-12
technical or customer support, xxxv
technical publications online or on the web,
-xxxix
TFSDIV (frame sync divisor) bit, A-45
THR register empty (THRE) flag, 11-4,
11-13
time division multiplexed (TDM) mode,
5-25, 5-27, 9-19, 10-15, 10-19
timeout, bus mastership, 3-87
timer expired (TIMEXP) pin, 14-8
timers, UART, 11-1
timing
definitions, 14-29
external memory accesses, 3-36
IDP hold timing mode 00, 7-13
IDP hold timing mode 01, 7-14
IDP I
2
S, 7-7
IDP left-justified sample pair, 7-7
PDAP, 7-14
SDRAM, 3-74
specifications, system design, 14-28
SPI clock, 6-5
SPI transfer protocol, 6-28, 6-29
timing (continued)
SPORT framed vs. unframed data, 5-40
SPORT left-justified sample pair mode,
5-19
SPORT normal vs. alternate framing,
5-40
SPORT word select, 5-25
TIMOD (SPI transfer initiation mode) bit,
6-10, 6-34
TMS (test mode select) pin, 14-12
TMZHI (timer expired high priority) bit,
B-15, B-19, B-23
TMZLI (timer expired low priority) bit,
B-17, B-21, B-25
transfer control block (TCB), 2-16
transfer initiation and interrupt (SPI
TIMOD) mode, 6-34
transferring data words, 5-4
transmission error (SPI TUNF) bit, 6-37
transmit and receive channel order (FRFS),
5-18, 5-23
transmit and receive data buffers
(TXSPxA/B, RXSPxA/B), 5-67
transmit collision error (SPI TXCOL) bit,
6-37
transmit data (SPI TXSPI) buffer, 6-2
transmit frame sync divisor. See TFSDIV
bit
transmit shift register (SPI TXSR), 6-2
TRST
(test reset) pin, 14-12
TUNF (SPI transmission error) bit, 6-37
TUVF_A (channel error status) bit, 5-65,
A-40
TWI controller
architecture, 12-2
block diagram, 12-3
bus arbitration, 12-12
call address, 12-14
clocking, 12-11
fast mode, setting, 12-14