Analog Devices SHARC ADSP-21368 - Page 888

Index
I-32 ADSP-21368 SHARC Processor Hardware Reference
SRC (continued)
sample rate ratio, 10-2, 10-19
sample rates, input, 10-18
servo loop, 10-2
time division multiplexing mode, 10-16,
10-18
tracking input and output rates, 10-2
SRC bits
auto hard mute
(SRCx_AUTO_MUTE), A-98,
A-103
bypass SRC (SRCx_BYPASS), A-99,
A-104
de-emphasis filter select
(SRCx_DEEMPHASIS), A-99,
A-104
dither select (SRCx_DITHER), A-99,
A-104
hard mute (SRCx_HARD_MUTE),
A-98, A-103
match phase mode select
(SRCx_MPHASE), A-100, A-105
output word length (SRCx_LENOUT),
A-100, A-105
serial input format (SRCx_SMODEIN),
A-99, A-104
serial output format
(SRCx_SMODEOUT), A-99, A-104
soft mute (SRCx_SOFTMUTE), A-99,
A-104
SRC enable (SRCx_ENABLE), A-100
SRU
bidirectional pin buffer, 4-13
buffers, 4-13
connecting peripherals with, 4-8
connecting through, 4-15
connection to precision clock generator
(PCG), 13-1
group A (clock) signals, 4-19, 4-52
group B (data) signals, 4-25
SRU (continued)
group C (frame sync) signals, 4-31
group D (pin assignments) signals, 4-36
group E (miscellaneous) signals, 4-43 to
4-46
group F signals, 4-47
inputs, 4-8
mnemonics, 4-9
naming conventions, 4-9
outputs, 4-8
register groups, 4-17
register use of, 4-15
serial ports and, 5-5
signal groups, 4-8, 4-18
SPORT connection example, 4-14, 4-16
SRU_CLKx (SRU clock) registers, 7-18,
7-21
SRU_DATx (SRU data) registers, 7-18,
7-21
SRU_PINGx_STAT (ping-pong DMA
status) register, A-110
SRU2
default configuration, 4-51
group A (input routing) signals, 4-52
group B (pin assingment) signals, 4-56
group C (pin enable) signals, 4-60
stack overflow/full interrupt (SOVFI) bit,
B-15, B-19, B-23
stall cycles, in IOP register access, 2-5
stalls, core, 14-54
stalls, execution, 14-53 to 14-56
standard DSP serial mode, 5-12
starting an interrupt driven transfer, 7-18,
7-20, 7-23
STATDAx (data memory breakpoint hit)
bit, A-181
STATI0 (I/O address breakpoint hit) bit,
A-181
STATIx (instruction address breakpoint
hit) bit, A-181