ADSP-21368 SHARC Processor Hardware Reference I-31
Index
SPORTs (continued)
interrupts, priority of, 5-72
latency in writes, 5-58
operation modes, 5-10, 5-11, 5-59
pairing, 5-27
primary and secondary data buffers, 5-4
pulse code modulation (PCM), 5-20
registers, listed, 5-50 to 5-58
reset, 5-71
serial clock pins, 5-6
setting frame sync rates, 5-17
setting word length, 5-17, 5-22
signal sensitivity, 5-9
signals, 5-6
SPORTx_DA and SPORTx_DB
channel data signal, 5-6
SPORTx_FS (serial port frame sync)
pins, 5-6
SPxI (serial port interrupt priority) bit,
5-72
standard DSP serial operation mode,
5-12
timing, left-justified sample pair mode,
5-19
timing, word select timing in I
2
S mode,
5-25
transferring data words, 5-4
transmit and receive data buffers, 5-4
Tx/Rx on FS falling, rising edge, 5-12,
A-30
Tx/Rx on FS rising edge, 5-12
using, 5-7
using with SRU, 5-5
word length, 5-43
word select timing in left-justified sample
pair mode, 5-19
SPORTs registers
control (SPCTLx), 2-26, 5-4, 5-6, 5-7,
5-59, 5-72
count (SPCNTx), A-45
SPORTs registers (continued)
divisor (DIVx), 5-6
DMA parameter, 5-76
modify (IMSPx), A-50
receive buffer (RXSPx), A-44
SPCTLx (serial port control), A-29
transmit buffer (TXSPx), A-43
transmit compand (MTxCSx,
MTxCCSx), A-47
SPTRAN (serial port data direction
control) bit, A-39
sample rate converter. See SRC
SRC
AD1896 core use with, 10-1
block diagram, 10-9
clocking, 10-15
configuring modes, 10-13, 10-21
control (SRCCTLx) register, 10-13,
10-21
data paths, 10-19
data ports and, 10-13, 10-21
de-emphasis (DEEMPHASIS) bits,
10-18
FIR filter, 10-2, 10-7, 10-10
frame sync signal, 10-18, 10-22
I
2
S, 10-14
input formats, A-99, A-104
MCLK (master clock), 10-2
mute (MUTE_OUT/MUTE_IN)
signals, 10-19
mute (SRCMUTE) register, 10-19,
10-21
muting, 10-19
normal, slow, fast modes, 10-11
parallel load shift register, 10-15
programming, 10-22
ratio (SRCRAT) register, 10-19, 10-21
registers, described, 10-21
right justified mode, 10-14
right-justified mode, 10-14, 10-18
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