Analog Devices SHARC ADSP-21368 - Page 886

Index
I-30 ADSP-21368 SHARC Processor Hardware Reference
SPORT bits (continued)
frame sync both (FS_BOTH), 5-64,
A-39
frame sync required (FSR), A-38
FS both enable (FS_BOTH), A-39
internal clock select (ICLK), 5-62, A-37
internal frame sync select (IFS), 5-63,
A-38
late frame sync (LAFS), A-38
left-justified sample pair mode control,
5-17
loopback mode (SPL), A-42
multichannel frame delay (MFD), A-42
multichannel mode enable (MCEA),
A-42
number of multichannel slots (NCH),
A-42
operation mode (OPMODE), 5-17
packing enable (PACK), A-37
receive underflow status (DERR_A,
ROVF_A or TUVF_A), A-40
serial word endian select (LSBF), 5-62,
A-37
serial word length (SLEN), 5-17, 5-62
serial word length select (SLEN), A-37
transmit underflow status (TUVF_A),
5-65, A-40
word packing enable (packing 16-bit to
32-bit words) PACK, 5-62
SPORT modes
I
2
S, 5-10, 5-20
I
2
S (Tx/Rx on left channel first), 5-11,
5-12, A-30
I
2
S (Tx/Rx on right channel first), 5-11,
5-12, A-30
left-justified sample pair, 5-12, 5-16,
5-18, 5-19, A-30
multichannel, 5-3, 5-25
multichannel, A and B channels, 5-12,
A-30
SPORT modes (continued)
operation mode (OPMODE) bit, 5-62
standard DSP, 5-11, A-30
SPORTs
See also SPORT bits, modes, registers
128-channel TDM, 5-4
16-bit to 32-bit word packing enable
(PACK), 5-62
bidirectional functions, 5-1
buffer, DMA, 5-15
buffers, using, 5-7
clock (SCLKx) pins, 5-6
companding (compressing/expanding),
5-2
configuring frame sync signals, 5-6
configuring standard DSP serial mode,
5-13
connections, 5-6
control (SPCTLx) registers, 5-59
DAI pin routing, 5-5
data buffers, 5-4
data types, 5-46
debugging, A-42
disabling the serial port(s), 5-72
DMA chaining, 5-81
DMA channels, 5-73, 5-74
enabling B channels, A-43
enabling I
2
S mode (OPMODE), 5-17,
5-22
enabling master mode (MSTR), 5-18
enabling SPORT DMA (SDEN), 5-19
features, 5-2
finding currently selected channel, A-43
frame sync rates, setting the internal
serial clock, 5-21
full-duplex operation, 5-6
I/O processor bus, 5-44
I
2
S control bits, 5-21
internal serial clock setting, 5-17
interrupts, 5-72, 5-75