Analog Devices SHARC ADSP-21368 - Page 878

Index
I-22 ADSP-21368 SHARC Processor Hardware Reference
restrictions (continued)
UART port controller, 11-11
right channel status for subframe B
(DIRCHANR) register, A-96
right-justify format (SPORTs)
companding, 5-61
setting, 5-46, A-37
rising and falling edge masks
digital audio interface, 4-70
rotating priority arbitration example, 3-86
rotating priority bus arbitration (RPBA)
pin, 3-81, 3-86
ROVF bit, 6-37
ROVF_A or TUVF_A (channel A error
status) bit, A-40
ROVF_A or TUVF_A (serial port error
status) bits, A-40
ROVF_B or TUVF_B (channel B error
status) bit, A-39
row addresses, 3-34
RS-232 device restrictions, 5-9
RSTI (reset interrupt) bit, B-14, B-19,
B-23
running reset, 14-22
running reset control register
(RUNRSTCTL), 14-25
RUNRSTIN (running reset input) signal,
14-12
RX_UACEN (DMA receive buffer enable)
bit, 11-12
RXFLSH (flush receive buffer) bit, 6-23,
6-25, 6-26
RXS (SPI data buffer status) bit, 6-30, A-57
RXSPI, RXSPIB (SPI receive buffer)
registers, 6-13, 6-37, A-59
RXSPI_SHADOW, RXSPIB_SHADOW
(SPI receive buffer shadow) registers,
A-59
RXSPx (serial port receive buffer) registers,
2-25, A-44
RXSR (SPI receive shift) register, 6-2
S
S/PDIF
audio standards, 9-16
biphase encoded data input, 9-18
biphase encoding, 9-11
BLK_START signal, 9-11
block structure, 9-2
channel status bit, 9-9
clock, 9-10
clock (SCLK) input, 9-10
DIR_I (receiver input) signal, 9-18
DIR_LRCLK_O (receiver frame sync
feed back out) signal, 9-19
DIR_LRCLK_REF_O (receiver frame
sync reference out) signal, 9-19
DIR_PLLCLK_I (External 512 x FS
(frame sync) PLL clock input) signal,
9-18
DIT_CLK_I (transmitter serial clock)
signal, 9-10
DIT_DAT_I (transmitter serial data)
signal, 9-10
DIT_EXT_SYNCEN signal, 9-11
DIT_FS_I (frame sync input to the
S/PDIF transmitter) signal, 9-10
DIT_HFCLK_I (transmitter over
sampling clock) signal, 9-11
DIT_O (transmitter biphase encoded
data stream) signal, 9-11
feed back out, 9-19
frame sync, 9-10
frame sync (LRCLK) input, 9-10
output routing, 9-8
oversampling clock, 9-11
PLL clock input, 9-18
preambles, 9-7
programming guidelines, 9-24
reference clock out, 9-19