Analog Devices SHARC ADSP-21368 - Page 877

ADSP-21368 SHARC Processor Hardware Reference I-21
Index
PWM (continued)
period (PWMPERIOD) registers, 8-5,
A-81
period completion status bits, 8-5
polarity select (PWMPOL) registers,
A-83
short-circuit condition, 8-6
single update mode, 8-15
status (PWMSTAT) register, A-81
switching dead time, 8-6
switching frequencies, 8-5
switching frequency equation, 8-5
three-phase timing unit, 8-7, 8-13
PWMAL, PWMBL (pulse width
modulation channel low duty control)
registers, A-84
PWMCTL (pulse width modulation
control) register, A-80
PWMGCTL (pulse width modulation
global control) register, A-78
PWMGSTAT (pulse width modulation
global status) register, A-79
PWMPERIOD (pulse width modulation
period) registers, A-81
PWMPOL (pulse width modulation
polarity select) registers, A-83
PWMSTAT (pulse width modulation
status) register, A-81
R
RAS definition, CBR (CAS before RAS),
3-33
read (RD
) pin, 3-21, 3-83
receive busy (overflow error) SPI DMA
status (SPIOVF) bit, 6-35, A-63
receive busy (overflow error) SPI status
(ROVF) bit, 6-37
receive data (RXSPI) buffer, 6-2
receive data buffer shadow
(RXSPI_SHADOW) register, A-59
receive data buffer status (RXS) bit, 6-30
receive data, serial port (RXSPx) registers,
2-25
receive data, SPI (RXSPI) register, 6-37
receive overflow error (SPIOVF) bit, 6-25,
6-26, 6-34
receive shift (RXSR) register, 6-2
reception error bit (ROVF, in SPI), 6-37
refresh rate in SDRAM, 3-50
register writes and effect latency (SPORT),
5-67
registers. See peripheral specific registers
related documents, xxxviii
reset
default settings, 14-3, 14-9
generators, 14-27
input hysteresis, 14-33
interrupt (RSTI) bit, B-14, B-19, B-23
partial, 14-22
pin, 14-20, 14-33
PLL startup, 14-19, 14-21
running, 14-22 to 14-26
running (RUNRST), 14-22
running reset control register
(RUNRSTCTL), 14-25
RESET
pin, 14-33
RESETOUT (reset output) signal, 14-12
restrictions
core hang in SPORTS, 5-7, 5-9
count (DMA) registers, 2-31
DMA, 2-47
external port, 3-94
I/O processor, 2-2, 2-31
idle cycle in page boundary, 3-22
PLL clock, 14-16
RESET
input, 14-33
RS-232, 5-9
SDRAM, 3-52
SPORTS read/write inactive buffer, 5-69
SPORTs SLEN value, 5-44