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Analog Devices SHARC ADSP-21368 - Page 876

Analog Devices SHARC ADSP-21368
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Index
I-20 ADSP-21368 SHARC Processor Hardware Reference
polarity (continued)
PWM single update mode, 8-9
SPDIF connections, 9-5
SPI clock, 6-21, 6-27
polling the I/O processor, 2-12
porting from previous SHARCs
paged DRAM boundary, 3-22
symbol changes, 1-12
post-modify, 14-53
power management control register
(PMCTL), A-170, A-172
power supply, monitor and reset generator,
14-28
power-up reset circuit, 14-27, 14-28
power-up sequence start, SDRAM
controller, 3-43
power-up, SDRAM (SDPM) bit, A-23
preambles, S/PDIF, 9-7
precharge command, 3-34
precision clock generators. See PCG
predictive reads, disable bit (NO_OPT),
A-19
printed circuit board design, 14-34
priority of the SPORT interrupts, 5-72
priority, rotating priority arbitration
example, 3-86
processor
architectural overview, 1-6
clock frequency, 5-1
core overview, 1-7
peripheral set by model, 1-5
product information, xxxvii
stalls, 14-52
product-related documents, xxxvii
program control interrupt (PCI) bit, 2-8,
2-16
program memory breakpoint hit
(STATPA) bit, A-181
programmable interrupt bits, B-6 to B-9
programmable interrupt registers (PICRx),
A-164 to A-170
programming examples
input data port, 7-31 to 7-33
power management, 14-14 to 14-16
precision clock generators, 13-23 to
13-25
SPORTs, 5-83 to 5-86
TWI controller, 12-15
programming guidelines, S/PDIF
transmitter, 9-24
pulse code modulation (PCM), 5-20
PWM
16-bit read/write duty cycle registers, 8-7
accuracy, 8-17
center-aligned modes, 8-3
center-aligned paired PWM
double-update mode, 8-11
channel duty control (PWMA, PWMB)
registers, A-84
channel low duty control (PWMAL,
PWMBL) registers, A-84
control (PWMCTL) register, A-80
control register use, 8-4
crossover mode, 8-16
dead time equation, 8-8
double update mode, 8-15
duty cycles, 8-8
edge-aligned mode, 8-3
emergency dead time, 8-13
equations, 8-5 to 8-12
full on to full off transition, 8-14
full on, off conditions, 8-12
global control (PWMGCTL) register,
A-78
global status (PWMGSTAT) register,
A-79
interrupts, 8-5
output control unit, 8-17
over-modulation, 8-12

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