Analog Devices SHARC ADSP-21368 - Page 875

ADSP-21368 SHARC Processor Hardware Reference I-19
Index
PCG (continued)
frame sync input source enable
(CLKx_SOURCE_IOP) bit, A-161
frame sync with external frame sync
enable (FSx_SYNC) bit, A-161,
A-162
frame syncs, 13-11
frequency of the frame sync output, 13-9
one shot frame sync A or B (STROBEx)
bits, 13-12
one shot option, 13-13
PCG_CTLA0 (control) register, A-156
phase shift of frame sync, 13-9
pulse width (PCG_PW) register, 13-11,
13-13
pulse width for frame sync (PWFSx) bit,
A-158
setup for I
2
S or left-justified DAI
example, 13-15
synchronization with the external clock,
13-7
PCI (program control interrupt) bit, 2-8,
2-16
PDAP, 7-8 to 7-14
(rising or falling) clock edge
(IDP_PDAP_CLKEDGE) bit, A-77
control (IDP_PP_CTL) register, 7-8,
A-74
data signal, 7-14
enable (IDP_PDAP_EN) bit, A-78
hold signal, 7-14
port mask bits (IDP_Pxx_PDAPMASK),
A-75
strobe, output, 7-14
timing, 7-14
PE (parity error) bit, 11-4
peripheral devices, I/O interface to, 5-1
peripheral DMA counter registers, 2-27
peripheral interrupt priority control
(PICR) registers, A-164
peripherals
memory mapped, 3-20
overview, 1-7
peripherals, processor specific, 1-5
phase shift of frame sync, 13-9
PICR (peripheral interrupt priority)
registers, A-164
ping-pong DMA, 7-22 to 7-24
pins
See also signals
ACK, enabling, A-18
data, function of, 14-7
descriptions, 14-2
external memory, 3-19
memory select (MSx
), 3-53
multiplexing, 14-2 to 14-12
open drain output, 6-9
pin states during SDRAM commands,
3-72
RESET
, 14-33
test clock (TCK), 14-12
test data input (TDI), 14-12
test data output (TDO), 14-12
test mode select (TMS), 14-12
test reset (TRST
), 14-12
plane, ground, 14-34
PLL programming restrictions, 14-16
PLL startup, 14-19, 14-21
PLL-based clocking, 14-13 to 14-19
PLLDx (PLL divider) bits, A-172
PLLM (PLL multiplier) bit, A-172
PMCTL (power management control)
register, A-170, A-172
polarity
clock polarity (CLKPL) bit, A-55
IDP encoding, 7-6
PWM configuration, 8-15
PWM double-update mode, 8-11
PWM polarity select registers
(PWMPOLx), A-83