Index
I-18 ADSP-21368 SHARC Processor Hardware Reference
MTxCSx (serial port transmit select)
registers, A-46
multichannel A and B channels, A-30
multichannel compand select (MTxCCSy
and MRxCCSy) registers, 5-47
multichannel operation (SPORT), 5-25
multichannel selection registers (SPORT),
5-31
multichannel, A and B channels, 5-12
multi-device SPI configuration, 6-12
multimaster conditions, 6-12
multimaster environment, 6-8
multiplexed (TDM) mode, time division,
9-19
multiplexing
in external port data pins, A-8
pins, 14-3 to 14-12
PWM pins, A-8
multiprocessing. See shared memory
N
negate breakpoint (NEGx) bit, A-175,
A-177
NINT (pending interrupt) bit, 11-10
non-chained DMA, 2-13
normal frame sync (SPORT), 5-40
normal interrupts, 4-65
O
OE (overrun error) bit, 11-4
one shot frame sync A or B (STROBEx)
bits, 13-12
one shot option (STROBEB) bit, 13-13
one shot, defined, 13-13
OPD (open drain output) pin, 6-9
OPMODE (SPORT serial port operation
mode) bit, 5-13, 5-17
OR, logical, 7-30, 9-24, A-175, A-177,
A-178
OSPID (operating system process ID), 2-4,
A-182
OSPIDENS (operating system process ID)
register enable bit, A-182
output control unit, PWM, 8-17
output pulse width, defined, 13-13
output strobe, PDAP, 7-14
over-modulation, PWM, 8-12
P
PACK (SPORT packing enable) bit, A-37
packing modes in PDAP, illustrated, 7-10
packing, data, 6-32
page size (SDRAM), A-25
page sizes in SDRAM, 3-34
parallel data acquisition port. See PDAP,
IDP
parallel input mode, 7-8
parameter registers, I/O processor, 2-25
PCG
active low frame sync select for frame
sync (INVFSx) bits, 13-12
bypass mode, 13-12
clock A source (CLKASOURCE) bit,
A-157
clock input (CLKIN) pin, 4-72, 13-2,
13-20
clock input source enable
(CLKx_SOURCE_IOP) bit, A-161
clock with external frame sync enable
(FSx_SYNC) bit, A-161
control (PCG_CTL_Ax) registers,
13-13, A-156
division ratios, 13-16
enable clock (ENCLKx) bit, A-156
enable frame sync (ENFSx) bit, A-156
frame sync A source (FSASOURCE) bit,
13-13, A-157
frame sync B source (FSBSOURCE) bit,
13-13, A-157