Analog Devices SHARC ADSP-21368 - Page 873

ADSP-21368 SHARC Processor Hardware Reference I-17
Index
M
making connections via the signal routing
unit, 4-15
manual
contents, xxxii
conventions, xliii
new in this edition, xxxiv
related documents, xxxviii
revisions, xxxiv
maskable interrupts, A-6
masking data (SDRAM), 3-33
master clock, external, 14-21
master input slave output (MISOx) pins,
6-2, 6-7, 6-8, 6-27
master mode enable (SPORT), 5-13, 5-29
master mode operation, SPI, 6-10
master out slave in (MOSIx) pin, 6-2, 6-7,
6-27
master-slave interconnections, 6-4
memory
boot memory, 3-30, 14-39
data transfer, FIFO, 7-16
internal banks, 3-33
memory banks, internal, 3-33
memory read RD
pin, 3-21, 3-83
memory select (flags) programming
(MSEN) bit, A-8
memory select (MSx
) pins, 3-21, 3-53,
3-83, 3-84, 3-89
memory transfer types, 2-1
memory-mapped emulation, breakpoint
registers, 2-4
memory-mapped IOP RXSPI buffer
registers, A-59
memory-to-memory DMA, 2-48
memory-to-memory DMA register, A-28
MISCAx_I (signal routing unit external
miscellaneous) register, 13-13
miscellaneous signals, 4-65
MISOx pins, 6-27
mode
broadcast (SPI), 6-8
chain insertion, 2-14, 2-41
chained DMA, 2-41
left-justified (SPORT), 5-16
left-justified sample pair (IDP), 7-3
loopback (SPORT), 5-6, A-42
master (SPI), 6-38
multichannel (SPORT), 5-3
open drain (SPI), 6-9
packing (IDP), 7-9, 7-10
right-justified (IDP), 7-3
self-refresh, 3-34
serial mode settings (IDP), 7-4
single channel double frequency
(S/PDIF), 9-8
standard serial (SPORT), 5-12
standard serial, signals (SPORT), 5-5
TDM (SPORT), 5-26
time division multiplexed (TDM), 9-19
two channel (SPDIF), 9-8
UART DMA, 2-44
UART non-DMA, 11-13
mode (SPDIF), two channel, 9-8
mode fault (multimaster error) SPI DMA
status (MME) bit, 6-35, 6-36
mode fault error (MME) bit, 6-9, 6-35,
6-36
mode register (SDRAM controller), 3-33
MOSIx pins, 6-27
MSBF (most significant byte first) bit, A-54
MSx
pins, memory select, 3-52, 3-53
MTM_FLUSH (memory-to-memory
FIFO flush) bit, 2-48
MTMDMACTL (memory-to-memory
DMA control) register, 2-48
MTxCCSx (serial port transmit compand)
registers, A-47
MTxCCSy and MRxCCSy (multichannel
compand select) registers, 5-47