Analog Devices SHARC ADSP-21368 - Page 872

Index
I-16 ADSP-21368 SHARC Processor Hardware Reference
interrupt mask (IMASK) control register,
B-18
interrupt vector, sharing, 5-72
interrupts, B-15, B-19, B-24
(enable RX status interrupt) bit, A-123
assigning priority for UART, 11-11
catastrophic, 4-65
conditions for generating interrupts in
SPORTs, 5-75
conditions, UART, 11-9
digital audio interface, 4-66, 7-22
digital peripheral interface, 4-67
I/O processor, using in the, 2-6
latch status for, B-13
listed in registers, B-1
non-maskable software (RSTI), A-6
normal, 4-65
UARTLSIE (enable UART RX status
interrupt) bit, 11-9
INVFSx (active low frame sync select for
frame sync) bits, 13-12
IOP register set, 5-49
IRPTL (interrupt latch) register, B-13
IRQ2-0
(hardware interrupt) pins, 14-8
IRQxI (hardware interrupt) bit, B-15,
B-16, B-19, B-20, B-24
ISSS (input service select) bit, A-58
J
jitter, clock, 14-33
JTAG interface pins, 14-12
L
LAFS (late transmit frame sync select) bit,
A-38
LAFS (SPORT late transmit frame sync
select) bit, 5-11, 5-14, 5-16, 5-20,
5-21, 5-40, 5-63, A-30, A-38
latching
high and low priority (DAI/DPI), 4-69
interrupt latch (IRPTL) register, B-13
status for interrupts, B-13
latchup, 14-32
latency
CAS, setting, 3-40
definition, CAS, 3-32
I/O processor registers, A-2
in SPORT registers, 5-58
input synchronization, 14-8
instruction fetch, external memory, 3-25
setting CAS, 3-40
left-justified data (S/PDIF), 9-7, 9-10
left-justified data (SRC), 10-13
framing, 10-17
matched-phase mode, 10-17
setting, 10-14
left-justified sample pair mode (IDP), 7-21
data transfer, core, 7-18
data transfer, DMA, 7-21
DMA, 7-26
FIFO data packing, 7-6
setting, 7-5
timing, 7-7
left-justified sample pair mode (SPORTs),
5-10, 5-16, 5-17
control bits, 5-17
Tx/Rx on FS falling edge, 5-12, A-30
Tx/Rx on FS rising edge, 5-12, A-30
left-justified waveform (PWM), 8-1
LIRPTL (interrupt) registers, 6-34, B-6
little endian (TWI controller), 12-9
loader kernel, 14-37
low active transmit frame sync (LFS, LTFS
and LTDV) bits, 5-63,
A-159
LRFS (SPORT logic level) bit, 5-29
LSBF (least significant bit first) bit, 5-62,
A-37