Analog Devices SHARC ADSP-21368 - Page 867

ADSP-21368 SHARC Processor Hardware Reference I-11
Index
external port (continued)
modes, setting, 3-24
read hold cycle (RHC) bits, A-19
external port bits
bank select (BxSD), A-11
bus priority (EPBR), A-12
data enable (DATA), A-13
delay line write pointer write back status
(WBS), A-16
DMA chain status (CHS), A-16
DMA chaining enable (CHEN), A-15
DMA channel priority, A-12
DMA circular buffer enable (CBEN),
A-15
DMA delay-line enable (DLEN), A-15
DMA direction (DMADR), A-15
DMA enable (DMAEN), A-15
DMA external interface status (EXTS),
A-16
DMA FIFO status (DFS), A-15
DMA flush FIFO (DFLSH), A-15
DMA transfer direction status (DIRS),
A-16
DMA transfer status (DMAS), A-15
flush tap list FIFO (TFLSH), A-15
freeze length (FRZDMA), A-12
freeze length core (FRZCR), A-12
tap list FIFO status (TFS), A-15
tap list loading status (TLS), A-16
external port control bus, 3-25, 3-26
external port DMA
chain pointer loading sequence, 2-37
chained, 2-36
channel priority, 2-35
delay line, 2-39
FIFO, 2-35
set up, 2-36
external port registers, A-10 to A-26
AMI control (AMICTLx), A-17
DMA control (DMACx), 2-26
external port registers (continued)
length and base (ELEP, EBEP), 2-37
F
FE (framing error) bit, 11-4
FIFO
control and status in input data port,
7-15
overflow clear bit, 7-15
to memory data transfer, 7-16
FIR filter in SRC, 10-2, 10-7
fixed-point overflow interrupt (FIXI) bit,
B-17, B-21, B-25
flag select bits (SPI), 6-10
flags
digital audio interface, 4-64
errors DMA, external port, host port,
serial port, SPI port, and UART port,
6-35
flag interrupt mode (IRQxEN) bits, A-7
input/output (FLAGx) pins, 6-4, 14-8
FLAGx pins, 6-4, 14-8
floating-point
compatibility, 1-3
FLTII (invalid operation interrupt) bit,
B-17, B-21, B-26
FLTOI (overflow interrupt) bit, B-17,
B-21, B-25
FLTUI (underflow interrupt) bit, B-17,
B-21, B-26
overflow interrupt (FLTOI) bit, B-17,
B-21, B-25
underflow interrupt (FLTUI) bit, B-17,
B-21, B-26
FLTII (floating-point invalid operation
interrupt) bit, B-21, B-26
formula, for frame sync pulse, 5-70
frame sync
A source (FSASOURCE) bit, A-157
active low vs. active high, 5-39