Index
I-12 ADSP-21368 SHARC Processor Hardware Reference
frame sync (continued)
both enable (FS_BOTH) bit, 5-64
early vs. late, 5-40
equations, 13-11
frequencies, 5-69
in multichannel mode, 5-28
internal vs. external, 5-38
options (FS_BOTH and DIFS), 5-18,
5-24
options (FS_BOTH), 5-18
output, synchronizing, 13-7
PCG B source (FSBSOURCE) bit,
13-13
signals, configuring, 5-6
SPORT frame on rising frame sync
(FRFS) bit, 5-17
SPORT frame sync required (FSR) bit,
5-63
frame sync rates
setting in SPORTs, 5-17, 5-21
setting the internal serial clock in
SPORTs, 5-21
framed versus unframed data in SPORTs,
5-37
framing bits, SPORT, 5-17
freezing, channel (in external port DMA),
3-18
frequencey mode, single-channel,
double-frequency, 9-8
frequency of the frame sync output, 13-9
full-duplex operation, specifications, 5-6
G
general-purpose (GPIO) and flags for
digital audio interface, 4-64
general-purpose IOP timer 2 interrupt
mask (GPTMR2IMSK) bit, B-10
general-purpose IOP timer interrupt mask
(GPTMRxIMSK) bits, B-10
generators, optional reset, 14-27
glitch vulnerability (SPORTs), 5-10
GM (get more data) bit, 6-11, 6-20, 6-37,
A-54
ground plane, in PCB design, 14-34
groupings of signals in DAI/DPI, 4-8
H
handshaking, external port, 3-20, 3-79
hardware interrupt
bits, B-15, B-16, B-19, B-20, B-24
signals IRQ2-0
, 14-4, 14-6, 14-8, B-16,
B-24
high and low priority latches, 2-7, 4-69
hold cycle (external bus) bit, A-18
hold cycles, external port, 3-23
hold off, processor bus transition, 3-84
hold time
inputs, 14-32
recognition of asynchronous input,
14-32
hold time cycles, setting, 3-23
hysteresis on RESET
pin, 14-33
I
I/O address breakpoint hit (STATI0) bit,
A-181
I/O interface to peripheral devices, 5-1
I/O processor
See also DMA; specific peripherals
address bus (IOA), 2-29
addressing in, 2-29
bandwidth, 2-12
baud rate, 2-43
bus arbitration and contention, 2-20
bus diagram, 2-25
bus grant, 2-21
chain insertion mode (DMA), 2-41
chain pointer (CPSPI) register, 2-16
chain pointer registers, 2-27, 2-43
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