Analog Devices SHARC ADSP-21368 - Page 869

ADSP-21368 SHARC Processor Hardware Reference I-13
Index
I/O processor (continued)
chained DMA, 2-14
configuring DMA, 2-2
count registers, 2-27, 2-31
DAI interrupt registers (DAI_IRPTL_H,
DAI_IRPTL_L), 2-7
data (IOD) bus, 2-20
data buffers in DMA, 2-32
DMA channel priority, 2-19
DMA channel registers, 2-32
DMA enable (DEN) bit, 2-48
DMA interrupt registers, 2-7
DMA interrupt vector locations, 2-8
DMA parameter registers, 2-17
DMA sequence complete interrupt, 2-8
external count (ECEPx) registers, 2-28
external index (EIPPx) registers, 2-27
external modify (EMEPx) registers, 2-28
interrupt driven I/O, 2-6
interrupt service routine restriction, 2-5
latency, 2-11 to 2-13
memory access, DMA, 2-8
polling driven I/O, 2-12
program control interrupt (PCI) bit, 2-8
regenerated interrupts, avoiding, 2-11
registers, listed, A-2
restrictions, 2-2, 2-31
restrictions (ISR), 2-5
stall conditions, 2-3
stall cycles in, 2-5
status driven I/O, 2-12
status polling, 2-12
transfer types, 2-1
type 1 or LW instructions, 2-2
I
2
C port. See TWI controller
I
2
S
(Tx/Rx on left channel first), 5-11, 5-12,
A-30
(Tx/Rx on right channel first), 5-11,
5-12, A-30
I
2
S (continued)
control bits, 5-21
example for DAI, 13-15
mode, 5-74
mode (IDP), 7-3, 7-5, 7-21
SPCTLx control bits, 5-22
timing (IDP), 7-7
transmit and receive channel order
(FRFS), 5-18, 5-23
ICLK (internal clock select) bit, A-37
identification (ID2-0) pin, 3-81
identification code (IDC) bit, 3-93, A-10
idle cycle (external bus) bit, A-19
idle cycle in external port, 3-22
IDP
(DAI) interrupt service routine
steps, 7-28
clocking select, 7-12
FIFO control, 7-15
FIFO memory data transfer, 7-16
FIFO status, 7-15
hold input, 7-12
illustrated, 7-1
interrupt-driven transfers, 7-17, 7-18
interrupts, 7-17, 7-19, 7-22, 7-24
masking, 7-9, A-74
memory data transfer, 7-16
packing modes, 7-9, 7-11
packing unit, 7-9
parallel input mode, 7-8
PDAP control (IDP_PP_CTL) register,
7-9
ping-pong DMA, 7-22 to 7-24
programming examples, 7-31
serial inputs, 7-3
serial modes, setting, 7-5
IDP bits
bus hang disable (IDP_BHD), 7-15,
7-19, A-67