Analog Devices SHARC ADSP-21368 - Page 870

Index
I-14 ADSP-21368 SHARC Processor Hardware Reference
IDP bits (continued)
clear buffer overflow (IDP_CLROVR),
7-15, 7-16, 7-25, A-67
DMA enable (IDP_DMA_EN), 7-20,
7-22, 7-25, A-67
DMA status (IDP_DMAx_STAT),
7-26, A-111
enable (IDP_ENABLE), 7-15, 7-18,
7-20, 7-22, 7-23, A-67
FIFO number of samples
(IDP_FIFOSZ), 7-15, 7-16, 7-19,
A-111
FIFO overflow (IDP_FIFO_OVER),
7-15, 7-16
FIFO overflow (SRU_OVF), 7-25
FIFO samples exceed interrupt
(IDP_FIFO_GTN_INT), 7-17,
7-19, A-113
frame sync format (IDP_SMODEx),
7-4, 7-18, 7-21, A-67, A-70
IDP_DMA_EN (DMA enable
restriction), 7-19
IDP_DMA_EN (input data port DMA
enable), 7-20
monitor number of samples
(IDP_NSET), 7-17, 7-18, 7-19, A-67
PDAP clock edge
(IDP_PDAP_CLKEDGE), 7-12,
7-18, 7-21, A-77
PDAP enable (IDP_PDAP_EN), 7-12,
7-22, A-78
PDAP input mask bits, 7-18
PDAP mask (IDP_Pxx_PPMASK), 7-9,
7-21, A-74
PDAP packing mode
(IDP_PDAP_PACKING), 7-9, A-77
PDAP reset (IDP_PDAP_RESET), 7-8,
A-78
ping-pong DMA enable (IDP_PING)
bits, A-68
IDP bits (continued)
port select (IDP_PORT_SELECT), 7-8,
7-18, 7-21, A-77
reset (IDP_PDAP_RESET) bit, A-78
IDP registers
control (IDP_CTL0), 7-18, 7-19, 7-20,
A-66
control (IDP_CTL1), 7-19, A-68
DMA control, 2-26, A-70
DMA count (IDP_DMA_Cx), 7-21,
7-28, A-71
DMA index (IDP_DMA_Ix), 7-21,
7-28, A-70
DMA modify (IDP_DMA_Mx), 7-21,
7-28, A-71
FIFO (IDP_FIFO), 7-15, 7-16, 7-17,
A-69
IDP_CTLx (input data port control),
7-18, 7-19, 7-20, A-66, A-68
IDP_DMA_AIx (ping-pong DMA
index), 7-23
IDP_DMA_PCx (ping-pong DMA
count), 7-23
PDAP control (IDP_PP_CTL), 7-8, 7-9,
7-12, A-74
ping-pong DMA count
(IDP_DMA_PCx) registers, 7-23
ping-pong DMA index
(IDP_DMA_AIx), 7-23
IFS (SPORT internal frame sync select) bit,
5-63, A-38
IICD (illegal input condition interrupt) bit,
B-15, B-19, B-23
IISPI (SPI DMA start address) register,
A-64
IISPx (serial port DMA internal index)
registers, 2-27, 2-29, A-50
illegal input condition detected (IICD) bit,
B-15, B-19, B-23
IMASK (interrupt mask) register, B-18