Index
I-10 ADSP-21368 SHARC Processor Hardware Reference
errors/flags, DMA, external port, host port,
serial port, SPI port, UART port, 6-35
examples
bidirectional DAI pin buffer, 4-13
DAI pin buffer, 4-10
DAI pin buffer output, 4-12
hold time in AMI, 3-24
idle cycle in AMI, 3-23
interrupt latency, regeneration, 2-11
PCG setup for I2S or left-justified DAI,
13-15
pin buffer, 4-10
PLL, 14-16
programming SPORTs (DMA
chaining), 5-83
programming SPORTs direct core
access, 5-86
programming SPORTs transmit
(DMA), 5-89
programming the IDP, 7-31 to 7-33
programming the PCG channels, 13-23
to 13-25
rotating priority arbitration, 3-86
SPI DMA chaining, 2-43
SRU1 connections for SPORTx, 4-14,
4-16
examples, timing
IDP hold timing mode 00, 7-13
IDP hold timing mode 01, 7-14
IDP I
2
S, 7-7
IDP left-justified sample pair, 7-7
PDAP, 7-14
SPI clock, 6-5
SPI transfer protocol, 6-28, 6-29
SPORT framed vs. unframed data, 5-40
SPORT left-justified sample pair mode,
5-19
SPORT normal vs. alternate framing,
5-40
SPORT word select, 5-25
execution stalls, bus transition, 3-84
external data path width, setting, 3-43
external master clock, 14-21
external memory
access timing, 3-36
address bank decoding, 3-53
banked, 3-30
banks, 3-30
external physical address, 3-29
interface, 3-20
most significant word first (MSWF) bit,
A-18
packing and unpacking (PKDIS) bits,
A-18
pin descriptions, 3-19
signals, 3-16, 3-20
external memory DMA
chained, setting up, 2-36
DMA count (ECEPx) registers, 2-28
DMA index (EIPPx) registers, 2-27
DMA modifier (EMEPx) registers, 2-28
external memory restrictions, 3-52
external port
buffer regsiter pipeline option, 3-45
bus hold cycle bit, A-18
bus idle cycle bit, A-19
chain pointer loading sequence, 2-38,
2-40
chain pointer register (CPEP), 2-36
channel freezing, 3-18
conflict resolution, 3-25
core address mapping, 3-52
data pin mode select (EPDATA) bits,
A-8
delay line DMA, 2-40
DMA, 2-35 to 2-40
DMA registers, A-14 to A-16
DMA throughput, 3-18
hold cycles, 3-23
modes, 3-24
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