ADSP-21368 SHARC Processor Hardware Reference I-9
Index
enable
breakpoint (ENBx) bit, A-178
clock outputs, 13-3
DMA, 7-20
DMA interrupt (INTEN) bit, 6-34
external port (asynchronous memory
interface), A-18
input data port, 7-15
multichannel mode in SPORTs, A-42
PCGs, 13-7
PDAP, 7-12
pulse width modulation groups, 8-4
sample rate converters, 10-22
SPDIF transmit buffer, 9-25
SPI DMA, 6-16
SPI slave, 6-20
SPORT DMA (SDEN bit), 5-24
SPORT master mode (MSTR), 5-18
enable receive buffer full interrupt (ERBFI)
bit, 11-7, A-123
enable transmit buffer empty interrupt
(ETBEI) bit, 11-7, A-123
endian format, 5-15, 5-45, 5-62, 6-1, A-37
enhanced emulation
feature enable (EEMUENS) bit, A-182
FIFO status (EEMUOUTFULLS) bit,
A-182
INDATA FIFO status
(EEMUINFULLS) bit, A-182
OUTDATA FIFO status
(EEMUOUTFULLS) bit, A-182
OUTDATA interrupt enable
(EEMUOUIRQENS) bit, A-181
OUTDATA ready (EEMUOUTRDY)
bit, A-181
equation
clock, 14-30
dead time, 8-8
duty cycles in PWM, 8-10
frame sync frequency, 5-71
equation (continued)
PWM dead time, 8-8
PWM switching frequency, 8-5
SDRAM refresh rate, 3-50
serial clock frequency, 5-70
serial port clock divisor, 5-70
SPI clock baud rate, A-60
TWI clock divider, 12-5
error signals and flags, 6-35
errors
clearing in SPI, 6-23
, 6-25
conditions in DAI/DPI, 4-71
data buffer status (SPORT), 5-65
data in SPORTs, 5-42
data truncation, 1-4
frame sync (SPORT), 5-26, 5-42
IDP FIFO, 7-15
internal bus (SDRAM), 3-71
PCG quantization, 13-2
preventing in DMA chaining, 2-16
reception (SPI), 6-37
S/PDIF error handling, 9-1, 9-22 to 9-23
S/PDIF receiver, 9-17
SDRAM, 3-77
SPI DMA, 6-14, 6-19
SPI master, 6-6
SPI mode fault, 6-36
SPI transmission, 6-21, 6-37
SPORT, 5-15
SRC, 10-3
SRC phase difference, 10-12
SRC resampling, 10-4
TWI master mode, 12-17, 12-18
TWI repeat start, 12-19
TWI slave transfer, 12-14, 12-16
UART, 11-4, 11-9
UART baud rate, 11-12
UART DMA, 2-46, 11-7
UART line, 11-7
UART sampling, 11-6
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