Quad Serial Peripheral Interface (QuadSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
998 Freescale Semiconductor
•9 Interrupt conditions
• The 9 interrupt conditions are mapped to 5 different interrupt lines
• Memory-mapped read access to flash memory content in separate address range:
— Supports flash devices of various sizes.
— Appropriate command sequence for flash read triggered automatically by read access.
• Automatic divide-by-2 of the serial flash device clock for commands not supporting the full
frequency range.
Additionally the following feature for power saving purposes is available independent from the external
device the QuadSPI is interfacing with:
• Support for global signal Stop mode
30.2.3 QuadSPI modes of operation
30.2.3.1 SPI Master mode
In the SPI Master mode the QuadSPI can initiate transmission and reception of serial data to/from the
external SPI device.Refer to Section 30.5.2.2, Master mode, for a detailed description. In this mode the
QuadSPI uses the system clock as its timing reference.
30.2.3.2 SPI Slave mode
The Slave mode allows the QuadSPI to communicate with an external SPI bus master. Refer to
Section 30.5.2.3, Slave mode, for a detailed description.
30.2.3.3 Serial Flash mode
In this mode an external serial flash memory device can be accessed. Further details about this mode of
operation can be found in Section 30.5.3, SFM (Serial Flash) mode. In this mode the QuadSPI uses the
auxiliary clock as its timing reference.
30.2.3.4 Module Disable mode
The Module Disable mode is used for power management of the device containing the QuadSPI module,
it is controlled by signals external to the QuadSPI. The clock to the non-memory mapped logic in the
QuadSPI can be stopped while in the Module Disable mode. See Section 30.5.4.1, Module Disable mode.
30.2.3.5 Stop mode
The Stop mode is also used for power management. When a request is made to enter Stop mode, the
QuadSPI block completes the action currently processed. Then the request is acknowledged.
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