NXP Semiconductors MPC5606S - Clock Gating

LIN Controller (LINFlex)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 877
• If 14.06% < D1 < 14.84%, LHE can be either set or reset depending on the dephasing between the
signal on LINFlex_RX pin the f
periph_set_1_clk
clock.
The second check is based on a measurement of time between each falling edge of the Synch Field:
•If D2 > 18.75%, LHE is set.
•If D2 < 15.62%, LHE is not set.
• If 15.62% < D2 < 18.75%, LHE can be either set or reset depending on the dephasing between the
signal on LINFlex_RX pin the f
periph_set_1_clk
clock.
Note that the LINFlex does not need to check if the next edge occurs slower than expected. This is covered
by the check for deviation error on the full synch byte.
23.8.2.5 Clock gating
The LINFlex clock can be gated from the Mode Entry module (see Chapter 25, Mode Entry Module
(MC_ME)). In LIN mode, the LINFlex controller acknowledges a clock gating request once the frame
transmission or reception is completed.
23.8.3 8-bit timeout counter
23.8.3.1 LIN timeout mode
Setting the LTOM bit in the LINTCSR enables the LIN timeout mode. The LINOCR becomes read-only,
and OC1[0:7] and OC2[0:7] output compare values in the LINOCR are automatically updated by
hardware.
This configuration detects header timeout, response timeout, and frame timeout.
Depending on the LIN mode (selected by the MME bit in LINCR1), the 8-bit timeout counter will behave
differently.
LIN timeout mode must not be enabled during LIN extended frames transmission or reception (that is, if
the data field length in the BIDR is configured with a value higher than 8 data bytes).
23.8.3.1.1 LIN Master mode
Field RTO[0:3] in the LINTOCR can be used to tune response timeout and frame timeout values. Header
timeout value is fixed to HTO[0:6] = 28-bit time.
Field OC1[0:7] checks T
Header
and T
Response
and field OC2[0:7] checks T
Frame
(refer to Figure 23-33).
When LINFlex moves from Break delimiter state to Synch Field state (refer to Section 23.7.2.3, LIN status
register (LINSR)):
• OC1[0:7] is updated with the value of OC
Header
(OC
Header
= CNT[0:7] + 28),
• OC2[0:7] is updated with the value of OC
Frame
(OC
Frame
= CNT[0:7] + 28 + RTO[0:6] × 9 (frame
timeout value for an 8-byte frame),
• the TOCE bit is set.